Time decay of magnetic properties in perpendicular magnetic recording media was studied. It was suggested that magnetization in media with a low energy ratio, KV/kT, of 50 is thermally stable in the absence of a demagnetizing field while coercivity exhibits a large time dependence. Magnetization in perpendicular recording media exhibited an appreciable time decay even for films with a large energy ratio of 300. The decay is attributed to the small perpendicular squareness due to a large perpendicular demagnetizing field acting in the media. The recording density dependence of the time decay in the output was explained in terms of the change in the demagnetizing field with the density. It is concluded that the use of media with large squareness as well as large energy ratio effectively reduces time decay in the output.

Obradovic and Parberry showed that any n-input k-ary function can be computed by a depth 4 unit-weight k-ary threshold circuit of size O(nkn). They also showed that any n-input k-ary symmetric function can be computed by a depth 6 unit-weight k-ary threshold circuit of size O(nk+1). In this paper, we improve upon and expand their results. The k-ary threshold circuits of nonunit weight and unit weight are considered. We show that any n-input k-ary function can be computed by a depth 2 k-ary threshold circuit of size O(kn-1). This means that depth 2 is optimal for computing some k-ary functions (e.g., a PARITY function). We also show that any n-input k-ary function can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(kn). Next, we show that any n-input k-ary symmetric function can be computed by a depth 3 k-ary threshold circuit of size O(nk-1), and can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(knk-1). Finally, we show that if the weights of the circuit are polynomially bounded, some k-ary symmetric functions cannot be computed by any depth 2 k-ary threshold circuit of polynomial-size.

A model for estimating the bending loss of 1.3 µm zero-dispersion single-mode fibers at 1.58 µm from the value at 1.55 µm is investigated experimentally and theoretically. An approximated equation for estimating the bending loss ratio of 1.58 µm to 1.55 µm is proposed, which provides good agreement with the experimental results.

The key concept of Physical Optics (PO), originally developed for a perfectly electric conductor (PEC), consists in that the high frequency fields on the scatterer surface are approximated by those which would exist on the infinite flat surface tangent to the scatterer. The scattered fields at arbitrary observation points are then calculated by integrating these fields on the scatterer. This general concept can be extended to arbitrary impedance surfaces. The asymptotic evaluation of this surface integration in terms of diffraction coefficients gives us the fields in analytical forms. In this paper, uniform PO diffraction coefficients for the impedance surfaces are presented and their high accuracy is verified numerically. These coefficients are providing us with the tool for the mechanism extraction of various high frequency methods such as aperture field integration method and Kirchhoff's method.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) with short channel effects, such as threshold voltage lowering and channel length modulation, is analyzed. First, new threshold voltage model of FD-SGT, which takes threshold voltage lowering caused by decreasing channel length into consideration, are proposed. We express surface potential as capacitance couple between channel and other electrodes such as gate, source and drain. And we analyze how surface potential distribution deviates from long channel surface potential distribution with source and drain effects when channel length becomes short. Next, by using newly proposed model, current-voltage characteristics equation with short channel effects is analytically formulated for the first time. In comparison with a three-dimensional (3D) device simulator, the results of newly proposed threshold voltage model show good agreement within 0.011 V average error. And newly formulated current-voltage characteristics equation also shows good agreement within 0.95% average error. The results of this work make it possible to clear the device designs of FD-SGT theoretically and show the new viewpoints for future ULSI's with SGT.

This paper presents a 4-valued content-addressable memory (CAM) for fully parallel template-matching operations in real-time cellular logic image processing with fixed templates. A universal literal is essential to perform a multiple-valued template-matching operation. It is decomposed of a pair of a threshold operation in a CAM cell and a logic-value conversion shared by CAM cells in the same column of a CAM cellular array, which makes a CAM cell function simple. Since a threshold operation together with a 4-valued storage element can be designed by using a single floating-gate MOS transistor, a high-density 4-valued universal-literal CAM with a single-transistor cell can be implemented by using a multi-layer interconnection technology. It is demonstrated that the performance of the proposed CAM is much superior to that of conventional CAMs under the same function.

A steady-state current-voltage characteristics of fully-depleted surrounding gate transistor (FD-SGT) is analyzed. First, the new gate oxide capacitance model and the new threshold voltage model of FD-SGT are proposed. It is shown that the gate oxide capacitance per unit area increases with scaling down the silicon pillar's diameter. It is newly found that the threshold voltage decreases with scaling down the silicon pillar's diameter, because the gate oxide electric fields increase with increasing gate oxide capacitance. Next, by using the proposed models, the new current-voltage characteristics equation of FD-SGT is analytically formulated for the first time. In comparison with the results of the three-dimensional (3D) device simulator, the results of the new threshold voltage model show good agreement within 0.012V error in maximum. The results of the newly formulated current-voltage characteristics also show good agreement within 1.4% average error. The results of this work make it possible to theoretically clear the device designs of FD-SGT and show the new viewpoints for future ULSI's with SGT.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

The problem of large power dissipation in the conventional Neuron MOS (νMOS) inverter has been resolved by introducing a newly developed deep threshold νMOS inverter. This deep threshold νMOS inverter has a very simple circuit configuration composed of a νMOS inverter using deep-threshold NMOSFET and PMOSFET and two-staged CMOS inverter. Circuit configuration optimization has been conducted by HSPICE simulation. As a result, the power dissipation in the new νMOS inverter has been reduced by a factor of 1/30 as compared to conventional νMOS inverter while the delay-time has been increased only by a factor of 3. The number detector designed with new νMOS gate has 1/6 of the power-delay product and 1/3.5 of the layout area as compared to the implementation by regular CMOS gate.

We have been studying on subthreshold characteristics of SOI (Silicon-On-Insulator) MOSFET's in terms of substrate bias dependence using a one-dimensional subthreshold device simulator based on Poisson equation in an SOI multilayer structure for estimating structural parameters of real devices. Here, we consider the quantum mechanical effects in the electron inversion layer of thin SOI MOSFET's, such as the two-dimensionally quantized electron states and transports, with a self-consistent solver of Poisson and Schrodinger equations and a mobility model by the relaxation time approximation. From results of simulations, we found a significant difference between this model and the classical model and concluded that the quantum mechanical effects need to be considered in analizing thin-film SOI devices.

To enhance fabrication yield for processor arrays, many reconfiguration schemes for replacing faulty processing elements (PE's) with spare PE's have been proposed. An array grid model based on single-track switches is one of such models. For this model, some algorithms for reconfiguring processor arrays have been proposed. However, any algorithm which can reconfigure the array, whenever the array is reconfigurable, has not been proposed as yet. This paper describes reconfiguration methods of processor arrays with faulty PE's. The methods use indirect replacements for reconfiguring arrays. First, we introduce a concept of fatal fault pattern, which makes an array unreconfigurable. Then, for the reconfiguration method with fixed spare arrangement, efficient spare arrangements are given by evaluating the probability of an occurring fatal fault pattern. Furher, we present reconfiguration algorithm with relocating spare. In the algorithm, fatal fault patterns are eliminated by relocating spare. Computer simulations show that the method has good performance of reconfiguration.

We discuss a new decoder for the multiple-valued signed-digit number, using a current-mode CMOS transistor-oriented circuit structure. In this paper, a new decoding method with the selective summation of a redundantly represented addend "O = [-1 r]" is proposed, where r is the radix and the addend is applied to each digit with a negative value and any consecutively higher digit takes which has a value of O. A newly designed literal linear circuit is realized, which has a current-switch function that makes independently the short path when each digit has a value of O. Through the parallel connections of these current swiches, the same addend signal at the lower digit is transmitted in a higher speed, The decoder circuit is tested by using the general circuit simulation software SPICE and the circuit characteristics of the selective summation of a redundantly represented O addend and the output results of the SD decoding operation were simulated. We also evaluated the decoder circuit in terms of the processing speed and the circuit size.

Extremely compact multi-mode interference (MMI) devices using central wide-angle coupling of input and output waveguides are proposed. It is shown that MMI can be used to change the propagation direction of light without the need for corner mirrors or bent waveguides. The concept can also be used for very compact power splitters which are even smaller than conventional MMI power splitters. Coupling between waveguides at wide angles is discussed and a number of regularities are found. The results can be useful for the design of more compact integrated circuits by a reduction of the number of bent waveguides which usually take up the largest part of the area of a photonic integrated circuit.

Theoretical values of site attenuation for broadband receiving antenna or the antenna factor of broadband antenna over the frequency range from 30 MHz to 1 GHz have been calculated or measured by some researchers. For a frequency range over 1 GHz, wire antennas or horn antennas should be used. However, the theoretical site attenuation or antenna factor over 1 GHz have never yet been calculated. A CLS (Conical Log-periodic Spiral) antenna is generally used for EMC/EMI measurements in the microwave band as a broadband wire antenna for the swept frequency method. However, this antenna has the defect that its use results in the loss of polarization information. So we proposed an improved CLS antenna which has linear polarization. This new CLS antenna has another wire wound symmetrically to that of the standard CLS antenna. For this reason, we named it a double-wire CLS antenna. The double-wire CLS antenna loses no polarization information. We calculated the height pattern and the frequency characteristics of CSA (Classical Site Attenuation) for the double-wire CLS antenna when used for receiving, or used for both transmitting and receiving, as well as the antenna factor. Moreover, NSA (Normalized Site Attenuation) when the double-wire CLS antenna is used for receiving or used for both transmitting and receiving in free space were calculated.

The Multiple input-output INverse/filtering Theorem (MINT) proves that N + 1 inverse filters are necessary to precisely control sound at N points in a space, and gives the minimum orders of such filters. In this paper, we propose the Indefinite MINT Filters (IMFs) for adding one or more control points to the above framework without increasing the number of inverse filters. Although the controllability of the new point is not sufficient, that of the other points is still maintained high enough by the principle of the MINT. In a two point sound control (using two inverse filters), the IMFs could reduce the squared error to the desired sound up to - 10 dB at the second point which is not controlled by the MINT.

Recently several dosimetric assessment procedures have been proposed to demonstrate the compliance of handheld mobile telecommuications equipment (MTE) with safety limits. However, for none of these procedures has an estimation of the overall uncertainty in assessing the maximum exposure been provided for a reasonable cross-section of potential users. This paper presents a setup and procedure based on a high-precision dosimetric scanner combined with a new phantom derived from an anatomical study. This allows the assessment of the maximum spatial peak SAR values occurring in approximately 90% of all MTE users, including children, with a precision of better than 25%. This setup and procedure therefore satisfies the requirements of the FCC, as well as those drafted by a CENELEC working group mandated by the European Union.

A detailed investigation of the electromagnetic field distributions inside waveguide circuits is useful for physical understanding, studies of electromagnetic coupling effects for EMC and EMI and for optimization of waveguide circuit designs. In this paper, we describe how to calculate and measure the two-dimensional electromagnetic field distributions inside waveguide-type planar circuits, making use of an analogy between H-plane waveguide- and trough-type surface-wave planar circuits. The measurement results are in good agreement with the results of the numerical analysis based on the normal mode expansion method.

In this paper, we give a new lower bound for the dimension of subfield subcodes. This bound improves the lower bound given by Stichtenoth. A BCH code and a subfield subcode of algebraic geometric code on a hyper elliptic curve are discussed as special cases.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

We extend the Rabin cryptosystem to the Eisenstein and Gauss fields. Methods for constructing the complete representation class and modulo operation of the ideal are presented. Based on these, we describe the methods of encryption and decryption. This proposed cryptosystem is shown to be as intractable as factorization, and recently presented low exponent attacks do not work against it.