This paper presents an efficient algorithm for large-scale multi-system learning task. The proposed architecture, referred to as the 'RBF×SOM', is based on the SOM2, that is, a'SOM of SOMs'. As is the case in the modular network SOM (mnSOM) with multilayer perceptron modules (MLP-mnSOM), the aim of the RBF×SOM is to organize a continuous map of nonlinear functions representing multi-class input-output relations of the given datasets. By adopting the algorithm for the SOM2, the RBF×SOM generates a map much faster than the original mnSOM, and without the local minima problem. In addition, the RBF×SOM can be applied to more difficult cases, that were not easily dealt with by the MLP-mnSOM. Thus, the RBF×SOM can deal with cases in which the probability density of the inputs is dependent on the classes. This tends to happen more often as the input dimension increases. The RBF×SOM therefore, overcomes many of the problems inherent in the MLP-mnSOM, and this is crucial for application to large scale tasks. Simulation results with artificial datasets and a meteorological dataset confirm the performance of the RBF×SOM.

The self-timed pipeline (STP) is one of the most promising VLSI/SoC architectures. It achieves efficient utilization of tens of billions of transistors, consumes ultra low power, and is easy-to-design because of its signal integrity and low electro-magnetic interference. These basic features of the STP have been proven by the development of self-timed data-driven multimedia processors, DDMP's. This paper proposes a novel scheme of interacting self-timed (clockless) pipelines by which the various distributed and interconnected pipelines can achieve highly functional stream processing in future giga-transistor chips. The paper also proposes a set of elementary coupling control modules that facilitate various combinations of flow-thru processing between pipelines, and then discusses the practicality of the proposed scheme through the LSI design of application modules such as a priority-based queue, a mutual interconnection network, and a pipelined sorter.

A 2.5 GHz 8-phase phase-locked loop (PLL) is proposed for 10-Gbps system on chip (SoC) transmission links application. The proposed PLL has several features which use new design techniques. The first one is a new variable delay cell (VDC) for the voltage control oscillator (VCO). Its advantages over the conventional delay cell are: wide-range output frequency and low noise sensitivity with low KVCO. The second feature is that, the PLL consists of a self-calibration circuit (SCC) which protects the PLL from variations in the process, voltage and temperature (PVT). The third feature is that, the proposed PLL has an 8-phase output frequency and also for avoiding the power/ground (P/G) effect and the substrate noise effect on the PLL, it also has a low jitter output frequency. The PLL is implemented in 0.13-µm CMOS technology. The PLL output jitter is 2.83 ps (rms) less than 0.7% of the output period. The total power dissipation is 21 mW at 2.5 GHz output frequency, and the core area is 0.08 mm2.

A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 8040 µm2. The active area of the PLL is 0.31 mm2.

This paper describes an analysis of the effects of electric field on nerve cells by using the Hodgkin-Huxley model. When evaluating our model, which combines an additional ionic current source and generated membrane potential, we derive the peak-to-peak value, the accumulated square of variation, and Kolmogorov-Sinai (KS) entropy of the cell-membrane potential excited by 10, 100, 1 k, and 10 kHz-sinusoidal electric fields. In addition, to obtain a comprehensive view of the time-variation patterns of our model, we used a self-organizing map, which provides a way to map high-dimensional data onto a low-dimensional domain. Simulation results confirmed that lower-frequency electric fields tended to increase fluctuations of the cell-membrane potential, and the additional ionic current source was a more dominant factor for fluctuations of the cell-membrane potential. On the basis of our model, we visually confirmed that the obtained data could be projected onto the map in accordance with responses of cell-membrane potential excited by electric fields, resulting in a combined depiction of the effects of KS entropy and other parameters.

In this study, I have numerically investigated the temperature distribution of n-type Si Nano Wire MOS Transistor induced by the self-heating effect by using a 3-D device simulator. The dependencies of temperature distribution within the Si Nano Wire MOS Transistor on both its gate length and width of the Si nano wire were analyzed. First, it is shown that the peak temperature in Si Nano Wire MOS Transistor increases by 100 K with scaling the gate length from 54 nm to 14 nm in the case of a 50 nm width Si nano wire. Next, it is found that the increase of its peak temperature due to scaling the gate length can be suppressed by scaling the size of the Si nano wire, for the first time. The peak temperature suppresses by 160 K with scaling the Si nano wire width from 50 nm to 10 nm in the case of a gate length of 14 nm. Furthermore, the heat dissipation in the gate, drain, and source direction are analyzed, and the analytical theory of the suppression of the temperature inside Si Nano Wire MOSFET is proposed. This study shows very useful results for future Si Nano Wire MOS Transistor design for suppressing the self-heating effect.

In this paper, Poly(3,4-ethylenedioxythiophene): Poly (Styrenesulfonate) (PEDOT:PSS) thin films for application in a bolometer, a type of uncooled infrared image sensor, are presented. In addition, the TCR and 1/f noise dependencies of PEDOT:PSS thin films on the thermal treatment conditions are demonstrated. It is also shown that an appropriate thermal treatment can suppress the 1/f noise of PEDOT:PSS thin films while maintaining the resistivity and TCR. A high TCR value over -4%/ (within 10 ohmcm) through chemical treatment is also presented. The results of this study show that PEDOT:PSS thin films have potential for use as a bolometric material.

Testing and diagnosis techniques play a key role in the advance of semiconductor memory technology. The challenge of failure detection has created intensive investigation on efficient testing and diagnosis algorithm for better fault coverage and diagnostic resolution. At present, March test algorithm is used to detect and diagnose all faults related to Random Access Memories. However, the test and diagnosis process are mainly done manually. Due to this, a systematic approach for developing and evaluating memory test algorithm is required. This work is focused on incorporating the March based test algorithm using a software simulator tool for implementing a fast and systematic memory testing algorithm. The simulator allows a user through a GUI to select a March based test algorithm depending on the desired fault coverage and diagnostic resolution. Experimental results show that using the simulator for testing is more efficient than that of the traditional testing algorithm. This new simulator makes it possible for a detailed list of stuck-at faults, transition faults and coupling faults covered by each algorithm and its percentage to be displayed after a set of test algorithms has been chosen. The percentage of diagnostic resolution is also displayed. This proves that the simulator reduces the trade-off between test time, fault coverage and diagnostic resolution. Moreover, the chosen algorithm can be applied to incorporate with memory built-in self-test and diagnosis, to have a better fault coverage and diagnostic resolution. Universities and industry involved in memory Built-in-Self test, Built-in-Self repair and Built-in-Self diagnose will benefit by saving a few years on researching an efficient algorithm to be implemented in their designs.

Arrayed waveguide grating (AWG) is a promising technology for constructing high-speed large-capacity WDM switches, because it can switch fast, is scalable to large size and consumes little power. To take the full advantage of high-speed AWG, the routing control of a massive AWG-based switch should be as simple as possible. In this paper, we focus on the self-routing design of AWG-based switches with O(1) constant routing complexity and propose a novel construction of self-routing AWG switches that can guarantee the attractive nonblocking property for both the wavelength-to-wavelength and wavelength-to-fiber request models. We also fully analyze the proposed design in terms of its blocking property, hardware cost and crosstalk performance and compare it against traditional designs. It is expected that the proposed construction will be useful for the design and all-optical implementation of future ultra high-speed optical packet/burst switches.

Privacy remains an issue for IT services. Users are concerned that their history of service use may be traceable since each user is assigned a single identifier as a means of authentication. In this paper, we propose a perfectly anonymous attribute authentication scheme that is both unidentifiable and untraceable. Then, we present the evaluation results of a prototype system using a PC and mobile phone with the scheme. The proposed scheme employs a self-blindable certificate that a user can change randomly; thus the certificate is modified for each authentication, and the authentication scheme is unidentifiable and untraceable. Furthermore, our scheme can revoke self-blindable certificates without leaks of confidential private information and check the revocation status without online access.

Halftoning is an important process to convert a gray scale image into a binary image with black and white pixels. The Direct Binary Search (DBS) is one of the well-known halftoning methods that can generate high quality binary images for middle tone of original gray scale images. However, binary images generated by the DBS have clippings, that is, have no tone in highlights and shadows of original gray scale images. The first contribution of this paper is to show the reason why the DBS generates binary images with clippings, to clarify the range of tone in original images that may have clipping, and to present a clipping-free DBS-based halftoning algorithm. The key idea is to apply the ordered dither using a threshold array generated by DBS-based method, to highlights and shadows, and then use the DBS. The second contribution is to extend the DBS to generate L-level multitone images with each pixel taking one of the intensity levels , , ..., . However, clippings appear in highlights, middle tone, and shadows of generated L-level multitone images. The third contribution of this paper is to modify the multitone version of the DBS to generate a clipping-free L-level multitone images. The resulting multitone images are so good that they reproduce the tones and the details of the original gray scale images very well.

As we scale toward nanometer technologies, the increase in interconnect parameter variations will bring significant performance variability. New design methodologies will emerge to facilitate construction of reliable systems from unreliable nanometer scale components. Such methodologies require new performance models which accurately capture the manufacturing realities. In this paper, we present a Linear Fractional Transform (LFT) based model for interconnect parametric uncertainty. The new model formulates the interconnect parametric uncertainty as a repeated scalar uncertainty structure. With the help of generalized Balanced Truncation Realization (BTR) and Linear Matrix Inequalities (LMI's), the porposed model reduces the order of the original interconnect network while preserves the stability. The LFT based new model even guarantees passivity if the BTR reduction is based on solutions to a pair of Linear Matrix Inequalities (LMI's) generated from Lur'e equations. In case of large number of uncertain parameters, the new model may be applied successively: the uncertain parameters are partitioned into groups, and with regard to each group, LFT based model is applied in turns.

Sensor networks have promising applications such as battlefield surveillance, biological detection, and emergency navigation, etc. Crucial problems in sensor networks are energy-efficiency and collision avoidance in wireless communication. To deal with the problems, we consider a self-stabilizing solution to the construction of k disjoint sense-sleep trees, where range adjustment and the use of GPS are allowed. Each root is determined by its identifier and is distinguished by its color, the identification of a tree. Using a dominating k-partition rule, each non-root node first determines a color irrelevant to the root. Then, the non-root node determines a parent node that is equally colored with minimal distance. If there is no appropriate parent, the range is extended or shrunk until the nearest parent is determined. Finally, we perform a simulation.

This paper proposes an efficient self-organizing map algorithm based on reference point and filters. A strategy called Reference Point SOM (RPSOM) is proposed to improve SOM execution time by means of filtering with two thresholds T1 and T2. We use one threshold, T1, to define the search boundary parameter used to search for the Best-Matching Unit (BMU) with respect to input vectors. The other threshold, T2, is used as the search boundary within which the BMU finds its neighbors. The proposed algorithm reduces the time complexity from O(n2) to O(n) in finding the initial neurons as compared to the algorithm proposed by Su et al. [16] . The RPSOM dramatically reduces the time complexity, especially in the computation of large data set. From the experimental results, we find that it is better to construct a good initial map and then to use the unsupervised learning to make small subsequent adjustments.

In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in line capacitance such as address lines, word lines, bit lines, and decoder. This paper presents ROM design of a novel HG (Half Grouping) compression method so as to reduce the parasitic capacitance of bit lines and the area of the row decoder for power consumption and chip area reduction. ROM design result of 512 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power, and 37.82% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented in a 0.35 µm CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply.

A desired property of large distributed systems is self adaptability against the faults that occur more frequently as the size of the distributed system grows. Self-stabilizing protocols provide autonomous recovery from finite number of transient faults. Fault-containing self-stabilizing protocols promise not only self-stabilization but also containment of faults (quick recovery and small effect) against small number of faults. However, existing composition techniques for self-stabilizing protocols (e.g. fair composition) cannot preserve the fault-containment property when composing fault-containing self-stabilizing protocols. In this paper, we present Recovery Waiting Fault-containing Composition (RWFC) framework that provides a composition of multiple fault-containing self-stabilizing protocols while preserving the fault-containment property of the source protocols.

We present a recovery scheme based on Self-protected Spanning Tree (SST), which recovers from failure all by itself. In the recovery scheme, the links are assigned birthdays to denote the order in which they are to be considered for adding to the SST. The recovery mechanism, named Birthday-based Link Replacing Mechanism (BLRM), is able to transform a SST into a new spanning tree by replacing some tree links with some non-tree links of the same birthday, which ensures the network connectivity after any single link or node failure. First, we theoretically prove that the SST-based recovery scheme can be applied to arbitrary two-edge connected or two connected networks. Then, the recovery time of BLRM is analyzed and evaluated using Ethernet, and the simulation results demonstrate the effectiveness of BLRM in achieving fast recovery. Also, we point out that BLRM provides a novel load balancing mechanism by fast changing the topology of the SST.

A self-stabilizing protocol is a protocol that achieves its intended behavior regardless of the initial configuration (i.e., global state). Thus, a self-stabilizing protocol is adaptive to any number and any type of topology changes of networks: after the last topology change occurs, the protocol starts to converge to its intended behavior. This advantage makes self-stabilizing protocols extremely attractive for designing highly dependable distributed systems on dynamic networks. While conventional self-stabilizing protocols require that the networks remain static during convergence to the intended behaviors, some recent works undertook the challenge of realizing self-stabilization in dynamic networks with frequent topology changes. This paper introduces some of the challenges as a new direction of research in self-stabilization.

For the purpose of the application of odor to information technology, we have developed an odor-emitting apparatus coupled with chemical capsules made of alginic acid polymer. This apparatus consists of a chemical capsule cartridge including chemical capsules of odor ingredients, valves to control odor emission, and a temperature control unit. Different odors can be easily emitted by using the apparatus. We have developed an integrated system of vision, audio and olfactory information in which odor strength can be controlled coinciding with on-screen moving images based on analytical results from the odor scanner.

We identify a broadband equivalent circuit of an on-chip self-complementary antenna integrated with a µm-sized semiconductor mesa structure whose circuit elements can be interpreted by using closed-form analysis. Prior to the equivalent circuit analysis, an electromagnetic simulation is done to investigate frequency independency of the input impedance for the integrated self-complementary antenna in terahertz range.