In the present paper, we address the problem of extrapolating group proximities from member relations, which we refer to as the group proximity problem. We assume that a relational dataset consists of several groups and that pairwise relations of all members can be measured. Under these assumptions, the goal is to estimate group proximities from pairwise relations. In order to solve the group proximity problem, we present a method based on embedding and distribution mapping, in which all relational data, which consist of pairwise dissimilarities or dissimilarities between members, are transformed into vectorial data by embedding methods. After this process, the distributions of the groups are obtained. Group proximities are estimated as distances between distributions by distribution mapping methods, which generate a map of distributions. As an example, we apply the proposed method to document and bacterial flora datasets. Finally, we confirm the feasibility of using the proposed method to solve the group proximity problem.

A novel half mode elliptic substrate integrated waveguide (HMESIW) filter with bypass coupling substrate integrated circular cavity (BCSICC) is proposed and fabricated by using standard PCB technology. Due to the use of an elliptical waveguide cavity, the tolerance sensitivity of the filter is reduced. The filter optimizing procedure is therefore simplified. The measured results demonstrate its superior performance in tolerance sensitivity and show good agreements with the simulation results.

In this paper, a sepic-type single-stage electronic ballast (STSSEB) is proposed, which is derived from the combination of a sepic converter and a half-bridge inverter. The ballast can not only step down input voltage directly but achieve high power factor, reduce voltage stress, improve efficiency and lower cost. Since component stress is reduced significantly, the presented ballast can be applied to high voltage mains. Derivation of the STSSEB is first presented. Then, analysis, design and practical consideration for the STSSEB are discussed. A 347 Vac 60 W prototype has been simulated and implemented. Simulations and experimental results have verified the feasibility of the proposed STSSEB.

The primary challenges faced by wireless sensor networks are how to construct the shortest spanning tree and how to determine the optimal sink node position in terms of minimizing the data transmission times and their variances for data gathering from all sensor nodes to a sink node. To solve these two problems, we propose a novel algorithm that uses the polygonal affine shortening algorithm with flow aggregation. This algorithm enables a wireless sensor network that has movable sensor nodes and one movable sink node to self-organize the shortest spanning tree and self-determine the optimal sink node position in a fully distributed manner. We also show that our algorithm is faster than the existing shortest path algorithm in terms of computational complexity.

Using a single-site lightning location technique, a new portable lightning location system is developed. We incorporate an attitude detection technique using inertial sensors to detect an accurate electromagnetic field vector of sferics by palm-sized electromagnetic sensors which can have arbitrary attitude. The present paper describes the concept and the performance of the developed prototype of the portable system.

In this letter, the diversity-multiplexing tradeoff (DMT) function for a special half-duplex dynamic decode and forward (DDF) relay protocol using two source-antennas, two destination-antennas, and more than two relay-antennas is derived. It is shown that the performance of the DDF relay protocol can be substantially improved by increasing the relay-antenna number, but only for low multiplexing gains.

Thin film glucose biosensors were fabricated with organic/inorganic hybrid films based on glucose oxidase (GOx) and Prussian Blue nano-clusters. The biosensors composed of hybrid films were characterized by the low operating potential and the advantage to interference-free detection. In this research, we employed two kinds of thin films for GOx immobilization: Langmuir-Blodgett (LB) and self-assembled monolayer (SAM). The LB film immobilizes GOx in its inside through the electrostatic force, while the SAM immobilizes GOx with the covalent bond. The sensors with LB film produced a relatively high current signal, while the non-linear behavior and a low stability were recognized. On the other hand, the sensors with SAM presented a good linear relationship and a very stable performance.

This paper studies the 2-adic complexity of the self-shrinking sequence under the relationship between 2-adic integers and binary sequences. Based on the linear complexity and the number of the sequences which have the same connection integer, we conclude that the 2-adic complexity of the self-shrinking sequence constructed by a binary m-sequence of order n has a lower bound 2n-2-1. Furthermore, it is shown that its 2-adic complexity has a bigger lower bound under some circumstances.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

Source coding theorem reveals the minimum achievable code length under the condition that the error probability is smaller than or equal to some small constant. In the single user communication system, the source coding theorem was proved for general sources. The class of general source is quite large and it is important result since the result can be applied for a wide class of sources. On the other hand there are several studies to evaluate the achievable code length more precisely for the restricted class of sources by using the restriction. In the multi-user communication system, although the source coding theorem was proved for general correlated sources, there is no study to evaluate the achievable code length more precisely. In this study, we consider the stationary memoryless correlated sources and show the coding theorem for Slepian-Wolf type problem more precisely than the previous result.

We propose frequency-domain optical code-division-multiplexing (CDM) employing quadrature-amplitude-modulation (QAM) using two of multi-level (M-ary) data generated based on electrical-domain spatial code spreading. Its spectral efficiency is enhanced compared to the conventional scheme with amplitude-shift-keying (ASK) using only one of M-ary data. Although it demands the recovery of amplitude and optical phase information, the practicality of the receiver is retained with self-homodyne detection using a phase-shift-keying (PSK) pilot light. Performance is theoretically evaluated and the optimal parameters are derived. Finally, the feasibility of the proposed technique is experimentally confirmed.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.

This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

We propose a novel method of supervised feature projection called class-distance-based discriminant analysis (CDDA), which is suitable for automatic age estimation (AAE) from facial images. Most methods of supervised feature projection, e.g., Fisher discriminant analysis (FDA) and local Fisher discriminant analysis (LFDA), focus on determining whether two samples belong to the same class (i.e., the same age in AAE) or not. Even if an estimated age is not consistent with the correct age in AAE systems, i.e., the AAE system induces error, smaller errors are better. To treat such characteristics in AAE, CDDA determines between-class separability according to the class distance (i.e., difference in ages); two samples with similar ages are imposed to be close and those with spaced ages are imposed to be far apart. Furthermore, we propose an extension of CDDA called local CDDA (LCDDA), which aims at handling multimodality in samples. Experimental results revealed that CDDA and LCDDA could extract more discriminative features than FDA and LFDA.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm2 and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

In this paper, a linear optimization of the dual-tree complex wavelet transform (DTCWT) based on the least squares method is proposed. The proposed method can design efficient DTCWTs by improving the design degrees of freedom and solving the least square solution iteratively. Because the resulting DTCWTs have good approximation accuracy of the half sample delay condition and the stopband attenuation, they provide precise shift-invariance and directionality. Finally, the proposed DTCWTs are evaluated by applying to non-linear approximation and image denoising, and showed their effectiveness, compared with the conventional DTCWTs.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.