This paper presents a novel disturb mitigation scheme which achieves low-energy operation for a deep sub-micron 8T SRAM macro. The classic write-back scheme with a dedicated read port overcame both half-select and read-disturb problems. Moreover, it improved the yield, particularly in the low-voltage range. The conventional scheme, however, consumed more power because of charging and discharging all write bitlines in a sub-block. Our proposed scheme reduces the power overhead of the write-back scheme using a floating write bitline technique and a low-swing bitline driver (LSBD). The floating bitline and the LSBD respectively consist of a precharge-less CMOS equalizer (transmission gate) and an nMOS write-back driver. The voltage on the floating write bitline is at an intermediate voltage between the ground and the supply voltage before a write cycle. The write target cells are written by normal CMOS drivers, whereas the write bitlines in half-selected columns are driven by the LSBDs in the write cycle, which suppresses the write bitline voltage to VDD - Vtn and therefore saves the active power in the half-selected columns (where Vtn is a threshold voltage of an nMOS). In addition, the proposed scheme reduces a leakage current from the write bitline because of the floating write bitline. The active leakage is reduced by 33% at the FF corner, 125. The active energy in the write operation is reduced by 37% at the FF corner. In other process corners, more writing power reduction can be expected because it depends on the Vtn in the LSBD. We fabricated a 512-Kb 8T SRAM test chip that operates at a single 0.5-V supply voltage. The test chip with the proposed scheme respectively achieves 1.52-µW/MHz writing energy and 72.8-µW leakage power, which are 59.4% and 26.0% better than those of the conventional write-back scheme. The total energy is 12.9 µW/MHz (12.9 pJ/access) at a supply voltage of 0.5 V and operating frequency of 6.25 MHz in a 50%-read/50%-write operation.

For large-scale sensor networks, multiple sinks are often deployed in order to reduce source-to-sink distance and thus cost of data delivery. However, having multiple sinks may work against cost reduction, because routes from sources can diverge towards different sinks which reduces the benefit of in-network data aggregation. In this letter we propose a self-clustering data aggregation protocol (SCAP) that can benefit from having multiple sinks as well as joint routes. In SCAP, nodes which detect the event communicate with each other to aggregate data between themselves, before sending the data to the sinks. The self-clustering extends network lifetime by reducing energy consumption of nodes near the sinks, because the number of paths in which the packets are delivered is reduced. A performance comparison with existing protocols L-PEDAP and LEO shows that SCAP can conserve energy and extend network lifetime significantly, in a multi-sink environment.

This paper presents a new common-mode stabilization method for a CMOS differential cascode Class-E power amplifier with LC-tank based driver stage. The stabilization method is based on the identification of the poles and zeros of the closed-loop transfer function at a critical node. By adding a series resistor at the common-gate node of the cascode transistor, the right-half-plane poles are moved to the left half plane, improving the common-mode stability. The simulation results show that the new method is an effective way to stabilize the PA.

Developing a rapid prototyping environment utilizing hardware description languages (HDLs) and conventional FPGAs can help ease and conquer the difficulties caused by the complexity of asynchronous digital systems and the advance of VLSI technology recently. We proposed a design flow and a FPGA template for implementing generalized C-element (gC) style asynchronous controllers. Utilizing conventional FPGA synthesis tools, self-timed bundled-data function modules can be realized with some effort on timing validation. The proposed design flow with FPGA-based realization approach is a very effective design methodology for rapid prototyping and functionality validation. This work could be useful for the early stage of performance estimation, power reduction exploration, circuits design training, and many other applications regarded asynchronous circuits. In this paper, the proposed FPGA-based asynchronous circuit design flow, a hands-on design tutorial, a generalized C-element template, and a list of synthesized benchmark circuits are documented and discussed in detail.

A 65 nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signaling allows the FPGA to operate at voltages down to 370 mV without any parameter tuning. We show both 2.6x total energy reduction and 6.4x performance improvement at the same time for energy minimum operation compared to the non-power gated SSFPGA, and compared to the latest research 1.8x improvement in power-delay product (PDP) and 2x performance improvement. When compared to a synchronous FPGA in a similar process we are able to show up to 84.6x PDP improvement. We also show energy minimum operation for maximum throughput on the power gated SSFPGA is achieved at 0.6 V, 27 fJ/operation at 264 MHz.

In this paper, for networked systems, synthesis of self-triggered controllers is addressed. In the proposed method, the control input and the sampling time such that a given cost function is minimized are computed simultaneously. First, the optimal control problem of continuous-time linear systems is rewritten as that of systems with integral continuous-time dynamics. Next, this problem is approximately reduced to a linear programming problem. The proposed method can be applied to model predictive control. Finally, the effectiveness of the proposed method is shown by a numerical example.

The susceptibility of a static random access memory (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90 nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

In this paper, the author proposes an electromagnetic coupling fed inverted-FL antenna design. The inverted-FL antenna with a self-complementary structure has been reported as a way to achieve a constant impedance of 188 ohms without the need for a matching load, since the axially symmetric self-complementary antenna has constant impedance, even though it has a finite structure. This design has been realized by integrating an inverted-F antenna with a self-complementary structure for achieving a broadband characteristic and an inverted-L element for operation on a frequency lower than the minimum frequency of the antenna. The proposed antenna realizes a broadband characteristic without attaching the matching load and the impedance transformer to match 50 ohms. The impedance transformer necessary for the inverted-FL antenna with a self-complementary structure is removed by using an electromagnetic coupling feed structure. This antenna, which has a volume of 101045 mm3, obtained broadband and multi-band characteristics covering the GSM850/GSM900/DCS/PCS/UMTS2100/UMTS2600 bands and the 2.5 G/3.5 G bands for Mobile-WiMAX in simulation and measurement.

In the present paper, we address the problem of extrapolating group proximities from member relations, which we refer to as the group proximity problem. We assume that a relational dataset consists of several groups and that pairwise relations of all members can be measured. Under these assumptions, the goal is to estimate group proximities from pairwise relations. In order to solve the group proximity problem, we present a method based on embedding and distribution mapping, in which all relational data, which consist of pairwise dissimilarities or dissimilarities between members, are transformed into vectorial data by embedding methods. After this process, the distributions of the groups are obtained. Group proximities are estimated as distances between distributions by distribution mapping methods, which generate a map of distributions. As an example, we apply the proposed method to document and bacterial flora datasets. Finally, we confirm the feasibility of using the proposed method to solve the group proximity problem.

A novel half mode elliptic substrate integrated waveguide (HMESIW) filter with bypass coupling substrate integrated circular cavity (BCSICC) is proposed and fabricated by using standard PCB technology. Due to the use of an elliptical waveguide cavity, the tolerance sensitivity of the filter is reduced. The filter optimizing procedure is therefore simplified. The measured results demonstrate its superior performance in tolerance sensitivity and show good agreements with the simulation results.

In this paper, a sepic-type single-stage electronic ballast (STSSEB) is proposed, which is derived from the combination of a sepic converter and a half-bridge inverter. The ballast can not only step down input voltage directly but achieve high power factor, reduce voltage stress, improve efficiency and lower cost. Since component stress is reduced significantly, the presented ballast can be applied to high voltage mains. Derivation of the STSSEB is first presented. Then, analysis, design and practical consideration for the STSSEB are discussed. A 347 Vac 60 W prototype has been simulated and implemented. Simulations and experimental results have verified the feasibility of the proposed STSSEB.

The primary challenges faced by wireless sensor networks are how to construct the shortest spanning tree and how to determine the optimal sink node position in terms of minimizing the data transmission times and their variances for data gathering from all sensor nodes to a sink node. To solve these two problems, we propose a novel algorithm that uses the polygonal affine shortening algorithm with flow aggregation. This algorithm enables a wireless sensor network that has movable sensor nodes and one movable sink node to self-organize the shortest spanning tree and self-determine the optimal sink node position in a fully distributed manner. We also show that our algorithm is faster than the existing shortest path algorithm in terms of computational complexity.

Using a single-site lightning location technique, a new portable lightning location system is developed. We incorporate an attitude detection technique using inertial sensors to detect an accurate electromagnetic field vector of sferics by palm-sized electromagnetic sensors which can have arbitrary attitude. The present paper describes the concept and the performance of the developed prototype of the portable system.

In this letter, the diversity-multiplexing tradeoff (DMT) function for a special half-duplex dynamic decode and forward (DDF) relay protocol using two source-antennas, two destination-antennas, and more than two relay-antennas is derived. It is shown that the performance of the DDF relay protocol can be substantially improved by increasing the relay-antenna number, but only for low multiplexing gains.

Thin film glucose biosensors were fabricated with organic/inorganic hybrid films based on glucose oxidase (GOx) and Prussian Blue nano-clusters. The biosensors composed of hybrid films were characterized by the low operating potential and the advantage to interference-free detection. In this research, we employed two kinds of thin films for GOx immobilization: Langmuir-Blodgett (LB) and self-assembled monolayer (SAM). The LB film immobilizes GOx in its inside through the electrostatic force, while the SAM immobilizes GOx with the covalent bond. The sensors with LB film produced a relatively high current signal, while the non-linear behavior and a low stability were recognized. On the other hand, the sensors with SAM presented a good linear relationship and a very stable performance.

This paper studies the 2-adic complexity of the self-shrinking sequence under the relationship between 2-adic integers and binary sequences. Based on the linear complexity and the number of the sequences which have the same connection integer, we conclude that the 2-adic complexity of the self-shrinking sequence constructed by a binary m-sequence of order n has a lower bound 2n-2-1. Furthermore, it is shown that its 2-adic complexity has a bigger lower bound under some circumstances.

Solution-based organic field-effect transistors (OFETs) with low parasitic capacitance have been fabricated using a self-aligned method. The self-aligned processes using a cross-linking polymer gate insulator allow fabricating electrically stable polymer OFETs with small overlap area between the source-drain electrodes and the gate electrode, whose frequency characteristics have been investigated by impedance spectroscopy (IS). The IS of polymer OFETs with self-aligned electrodes reveals frequency-dependent channel formation process and the frequency response in FET structure.

Source coding theorem reveals the minimum achievable code length under the condition that the error probability is smaller than or equal to some small constant. In the single user communication system, the source coding theorem was proved for general sources. The class of general source is quite large and it is important result since the result can be applied for a wide class of sources. On the other hand there are several studies to evaluate the achievable code length more precisely for the restricted class of sources by using the restriction. In the multi-user communication system, although the source coding theorem was proved for general correlated sources, there is no study to evaluate the achievable code length more precisely. In this study, we consider the stationary memoryless correlated sources and show the coding theorem for Slepian-Wolf type problem more precisely than the previous result.

We propose frequency-domain optical code-division-multiplexing (CDM) employing quadrature-amplitude-modulation (QAM) using two of multi-level (M-ary) data generated based on electrical-domain spatial code spreading. Its spectral efficiency is enhanced compared to the conventional scheme with amplitude-shift-keying (ASK) using only one of M-ary data. Although it demands the recovery of amplitude and optical phase information, the practicality of the receiver is retained with self-homodyne detection using a phase-shift-keying (PSK) pilot light. Performance is theoretically evaluated and the optimal parameters are derived. Finally, the feasibility of the proposed technique is experimentally confirmed.

This paper presents a low-power FPGA based on mixed synchronous/asynchronous design. The proposed FPGA consists of several sections which consist of logic blocks, and each section can be used as either a synchronous circuit or an asynchronous circuit according to its workload. An asynchronous circuit is power-efficient for a low-workload section since it does not require the clock tree which always consumes the power. On the other hand, a synchronous circuit is power-efficient for a high-workload section because of its simple hardware. The major consideration is designing an area-efficient synchronous/asynchronous hybrid logic block. This is because the hardware amount of the asynchronous circuit is about double that of the synchronous circuit, and the typical implementation wastes half of the hardware in synchronous mode. To solve this problem, we propose a hybrid logic block that can be used as either a single asynchronous logic block or two synchronous logic blocks. The proposed FPGA is fabricated using a 65-nm CMOS process. When the workload of a section is below 22%, asynchronous mode is more power-efficient than synchronous mode. Otherwise synchronous mode is more power-efficient.