This paper presents a self-timed SRAM system employing new memory segment technique that divides memory cell arrays into multiple regions based on its latency, not the size of the memory cell array. This is the main difference between the proposed memory segmentation technique and the conventional method. Consequently, the proposed method provides a more efficient way to reduce the memory access time. We also proposed an architecture of dummy cell and completion signal generator for the handshaking protocol. We synthesized a 8 MB SRAM system consisting of 16 512K memory blocks using Hynix 0.35-µm CMOS process. Our implantation shows 15% higher performance compared to the other systems. Our implementation results shows a trade-off between the area overhead and the performance for the number of memory segmentation.

This paper proposes a built-in self-test (BIST) scheme for noise-tolerant testing of a digital-to-analogue converter (DAC). The proposed BIST calculates the differences in output voltages between a DAC and test modules. These differences are used as the inputs of an integrator that determines integral nonlinearity (INL). The proposed method has an advantage of random noise cancelation and achieves a higher test accuracy than do the conventional BIST methods. The simulation results show high standard noise-immunity and fault coverage for the proposed method.

A 0.8-V CMOS Phase-Locked Loop (PLL) has been designed and fabricated by using a 0.13-µm 1p8m CMOS process. In the proposed PLL, the double-positive-feedbacks voltage-controlled oscillator (DPF-VCO) is used to generate current signals for the coupling current-mode injection-locked frequency divider (CCMILFD) and current-injection current-mode logic (CICML) divider. A short-pulsed-reset phase frequency detector (SPR-PFD) with the reduced pulse width of reset signal to improve the linear range of the PFD and a complementary-type charge pump to eliminate the current path delay are also adopted in the proposed PLL. The measured in-band phase noise of the fabricated PLL is -98 dBc/Hz. The locking range of the PLL is from 22.6 GHz to 23.3 GHz and the reference spur level is -69 dBm that is 54 dB bellow the carrier. The power consumption is 9.2 mW under a 0.8-V power supply. The proposed PLL has the advantages of low phase noise, low reference spur, and low power dissipation at low voltage operation.

We propose a novel method of supervised feature projection called class-distance-based discriminant analysis (CDDA), which is suitable for automatic age estimation (AAE) from facial images. Most methods of supervised feature projection, e.g., Fisher discriminant analysis (FDA) and local Fisher discriminant analysis (LFDA), focus on determining whether two samples belong to the same class (i.e., the same age in AAE) or not. Even if an estimated age is not consistent with the correct age in AAE systems, i.e., the AAE system induces error, smaller errors are better. To treat such characteristics in AAE, CDDA determines between-class separability according to the class distance (i.e., difference in ages); two samples with similar ages are imposed to be close and those with spaced ages are imposed to be far apart. Furthermore, we propose an extension of CDDA called local CDDA (LCDDA), which aims at handling multimodality in samples. Experimental results revealed that CDDA and LCDDA could extract more discriminative features than FDA and LFDA.

This brief paper describes a background calibration algorithm for a pipelined ADC with an open-loop amplifier using a Split ADC structure. The open-loop amplifier is employed as a residue amplifier in the first stage of the pipelined ADC to realize low power and high speed. However the residue amplifier as well as the DAC suffer from gain error and non-linearity, and hence they need calibration; conventional background calibration methods take a long time to converge. We investigated the split ADC structure for its background calibration with fast convergence, and validated its effectiveness by MATLAB simulation.

In this paper, a 65 nm 1.2 V 7-bit 1GSPS folding-interpolation A/D converter with a digitally self-calibrated vector generator is proposed. The folding rate is 2 and the interpolation rate is 8. A self-calibrated vector generation circuit with a feedback loop and a recursive digital code inspection is described. The circuit reduces the variation of the offset voltage caused by process mismatches, parasitic resistors, and parasitic capacitances. The chip has been fabricated with a 65 nm 1-poly 6-metal CMOS technology. The effective chip area is 0.87 mm2 and the power consumption is about 110 mW with a 1.2 V power supply. The measured SNDR is about 39.1 dB when the input frequency is 250 MHz at a 1 GHz sampling frequency. The measured SNDR is drastically improved in comparison with the same ADC without any calibration.

In this paper, a linear optimization of the dual-tree complex wavelet transform (DTCWT) based on the least squares method is proposed. The proposed method can design efficient DTCWTs by improving the design degrees of freedom and solving the least square solution iteratively. Because the resulting DTCWTs have good approximation accuracy of the half sample delay condition and the stopband attenuation, they provide precise shift-invariance and directionality. Finally, the proposed DTCWTs are evaluated by applying to non-linear approximation and image denoising, and showed their effectiveness, compared with the conventional DTCWTs.

Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as 'soft specifications', are defined.

A 60-GHz injection-locked frequency divider (ILFD) is presented. A multi-order LC oscillator topology is proposed to enhance the locking range of the divider. A design guideline is described based on a theoretical analysis of the locking range enhancement. A test chip is fabricated in 65 nm CMOS. Measured locking range with 0 dBm input power is 48.5–62.9 GHz (25.9%), which is 63.6% wider compared to the previously reported ILFD. Power consumption excluding buffers and biasing circuits is 1.65 mW from 1.2 V supply. The core ILFD area is 0.0157 mm2 even with an extra pair of inductors.

As the demand for spectrum for future wireless communication services increases, cognitive radio technology has been developed for dynamic and opportunistic spectrum access, which enables the secondary users to use the underutilized licensed spectrum of the primary users. In particular, the recent studies on the MAC protocol for dynamic and opportunistic access have focused on sensing and using the vacant spectrum efficiently. Under the ad-hoc network environment, how the secondary users use the unused channels by the primary users affects the efficient utilization of channels and a cognitive radio system is required to follow the rapid and frequent changes in channel status. In this paper, we propose a self-scheduling multi-channel cognitive MAC (SMC-MAC) protocol, which allows multiple secondary users to transmit data though the sensed idle channels by two cooperative channel sensing algorithms, i.e., fixed channel sensing (FCS) and adaptive channel sensing (ACS), and by slotted contention mechanism to exchange channel request information for self-scheduling. The performance of the proposed SMC-MAC protocol is investigated via analysis and simulations. According to the results, the proposed SMC-MAC protocol is effective in allowing multiple secondary users to transmit data frames effectively on multi-channels and adaptively in response to the primary users' traffic dynamics.

This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

This paper presents an improved version of multi-stage threshold decoding with a difference register (MTD-DR) for self-orthogonal convolutional codes (SOCCs). An approximate lower bound on the bit error rate (BER) with the maximum likelihood (ML) decoding is also given. MTD-DR is shown to achieve an approximate lower bound of ML decoding performance at the higher Eb/N0. The code with larger minimum Hamming distance reduces the BER in error floor, but the BER in waterfall shifts to the higher Eb/N0. This paper gives a decoding scheme that improves the BER in both directions, waterfall and error floor. In the waterfall region, a 2-step decoding (2SD) improves the coding gain of 0.40 dB for shorter codes (code length 4200) and of 0.55 dB for longer codes (code length 80000) compared to the conventional MTD-DR. The 2-step decoding that serially concatenates the parity check (PC) decoding improves the BER in the error floor region. This paper gives an effective use of PC decoding, that further makes the BER 1/8 times compared to the ordinary use of PC decoding in the error floor region. Therefore, the 2SD with effective use of parity check decoding improves the BER in the waterfall and the error floor regions simultaneously.

We consider RFID bookshelves, which detect the location of books using RFID. An RFID bookshelf has the antennas of RFID readers in the boards, and detects the location of an RFID tag attached to a book. However, the accuracy is not good with the experience of the existing system, and sometimes reads the tag of the next or even further area. In this paper, we propose a method to improve the location detection using naive Bayes classifer, and show the experimental result. We obtained 78.6% of F-measure for total 12658 instances, and show the advantage against the straightforward approach of calculating the center of gravity of the read readers. More importantly, we show the performance is less dependent of a change of layouts and a difference of books by leave-1-layout/book-out cross validation. This is favorable for the feasibility in library operation.

Due to the lack of end-to-end paths between the communication source and destination, the routing of Delay Tolerant Networks (DTN) exploits the store-carry-and-forward mechanism. This mechanism requires nodes with sufficient energy to relay and forward messages in a cooperative and selfless way. However, in the real world, the energy is constrained and most of the nodes exhibit selfish behaviors. In this paper, we investigate the performance of DTN routing schemes considering both the energy constraint and selfish behaviors of nodes. First, we model the two-hop relay and epidemic routing based on a two-dimensional continuous time Markov chain. Then, we obtain the system performance of message delivery delay and delivery cost by explicit expressions. Numerical results show that both the energy constraint and node selfishness reduce the message delivery cost at the expense of increasing the message delivery delay. Furthermore, we demonstrate that the energy constraint plays a more important role in the performance of epidemic routing than that of two-hop relay.

For the easy design of very small normal-mode helical antennas (NMHAs), an equation that helps determine the self-resonant structures of these antennas is developed. For this purpose, the expression for the capacitance of an NMHA is established. The accuracy of this design equation is confirmed by comparing the results obtained using the equation with the simulation results.

A new kind of 3D power divider based on a half-mode substrate integrated circular cavity (HSICC) is proposed. This novel power divider can reduce the size of a power divider based on normal substrate integrated circular cavity (SICC) by nearly a half. To verify the validity of the design method, a two-way X-band HSICC power divider using low temperature co-fired ceramic (LTCC) technology is designed, fabricated and measured.

A 1.8 V, 5 GHz low power frequency synthesizer for Wireless Sensor Networks is presented in 0.18 µm CMOS technology. A low power phase-switching prescaler is designed, and the current mode phase rotator is merged into the first divide-by-2 circuit of the prescaler to reduce power and propagation delay. An improved charge pump circuit is proposed to compensate for the dynamic effects with the charge pump. By a divide-by-2 circuit, the frequency synthesizer can provide a 2.324-2.714 GHz quadrature output frequency in 1 MHz steps with a 4 MHz reference frequency. The measured output phase noise is -110 dBc/Hz at 1-MHz offset frequency. The power consumption of the PLL is 11.2 mW at 1.8 V supply voltage.

We describe the fabrication processes and electrical characteristics of two types of NbN junctions. One is a self-shunted NbN/NbNx/AlN/NbN Josephson junction, which is expected to improve the density of integrated circuits; the other is an underdamped NbN/AlNx/NbN tunnel junction with radical-nitride AlNx barriers, which has highly controllable junction characteristics. In the former, the junction characteristics were changed from underdamped to overdamped by varying the thickness of the NbNx layer. Overdamped junctions with a 6-nm-thick NbNx film exhibited a characteristic voltage of Vc = 0.8 mV and a critical current density of Jc = 22 A/cm2 at 4.2 K. In the junctions with radical-nitride AlNx barriers, Jc could be controlled in the range 0.01-3 kA/cm2 by varying the process conditions, and good uniformity of the junction characteristics was obtained.

In this paper, an artificial sub-threshold oscillating spiking neuron is presented and its response phenomena to an input spike-train are analyzed. In addition, a dynamic parameter update rule of the neuron for achieving synchronizations to the input spike-train having various spike frequencies is presented. Using an analytical two-dimensional return map, local stability of the parameter update rule is analyzed. Furthermore, a pulse-coupled network of the neurons is presented and its basic self-organizing function is analyzed. Fundamental comparisons are also presented.

A hardware description languages (HDLs) based modeling technique for asynchronous circuits is presented in this paper. A HDLs handshake package has been developed for expressing handshake-style digital systems in both VHDL and Verilog. Burst-mode and extended burst-mode (BM/XBM) circuits were used to demonstrate the usefulness of this work. This research successfully prototyped comparators, adders, RSA encoder/decoder, and several self-timed circuits for the full-custom IC and FPGAs designs. Furthermore, the HDLs handshake package implemented by this research can be utilized to develop behavioral test benches for studying and analyzing asynchronous designs. Extracting detailed timing information from asynchronous finite state machines (AFSMs), detecting delay faults for synthesized self-timed functional modules, and locating fundamental mode violation within realized AFSMs are proven applications. The anticipated HDL modeling technique and the transformation procedure are detailed in the rest of this paper.