A priming effect is studied for a three-electrode, surface-discharge AC-PDP, which has stripe barrier ribs of 0.22 mm pitch. It was found that by keeping the interval between the reset and address pulses within 24 µs, the data pulse voltage can be reduced while the data pulse width can be narrowed due to the priming effect. By adopting the primed addressing technique to the PDP, the data pulse voltage was reduced to 20 V when the data and scan pulse widths were 1 µs. Alternatively, the data pulse width could be narrowed to 0.33 µs when the data pulse voltage was 56 V. 69% of the TV field time could be assigned for the display periods with 12 sub-fields, assuring high luminance display.

This work provides a generalization of structural logic optimization methods to general boolean networks. This generalization is based on a functional description of the nodes in the network. Therefore, this approach is no longer restricted to networks that consist of simple gates. Within this framework, we present necessary and sufficient conditions to identify all the possible functional expansions of a node that allow to eliminate a wire elsewhere in the network. These conditions are also given for the case of multiple variable expansion, providing an incremental mechanism to perform functional transformations involving any number of variables that can be applied in a very efficient manner. On the other hand, we will show in this paper that relevant simplifications can be obtained when this framework is applied to the particular case of AND-OR-NOT networks, resulting in important savings in the computational effort. When compared to previous approaches, the experimental results show an important reduction in the number of computations required.

In this paper, a LSI design for video encoder and decoder for H.263+ video compression is presented. LSI operates under clock frequency of 27 MHz to compress QCIF (176144 pixels) at the frame rate of 30 frame per second. The core size is 4.6 4.6 mm2 in a 0.35 µm process. The architecture is based on bus connected heterogeneous dedicated modules, named as System-MSPA architecture. It employs the fast and small-chip-area dedicated modules in lower level and controls them by employing the slow and flexible programmable device and an external DRAM. Design results in success to achieve real time encoder in quite compact size without losing flexibility and expand ability. Real time emulation and easy test capability with external PC is also implemented.

An advanced spare-connection scheme for K-out-of-N redundancy is proposed for constructing fault-tolerant ring- or toroidal mesh-connected processing-node arrays able to enhance emulation of binary hypercubes by using bypass networks. With this scheme, a component redundancy configuration for a base array with a fixed number of primary nodes, such as that for 8-node ring or 32-node toroidal mesh, can be constructed by using bypass links with a segmented bus structure to selectively connect the primary nodes to a spare node in parallel. These bypass links are allocated to the primary nodes by graph-node coloring with a minimum inter-node distance of three in order to use the bypass links as the hypercube connections as well as to attain strong fault tolerance for reconfiguring the base array with the primary network topology. An extended redundancy configuration for a large fault-tolerant array can be constructed by connecting the component configurations by using external switches of a hub type provided at the bus nodes of the bypass links. This configuration has a network topology of the parallel star-connections of sub-hypercubes whose diameter is smaller than that of the regular hypercube.

Boundary Constraints of VLSI floorplanning require a set of blocks to be placed along the boundaries of the chip. Thus, this set of blocks can be adjacent to I/O pads for external communication. Furthermore, these blocks are kept away from the central area so that they do not form blockage for internal routing. In the paper, we devise an algorithm of VLSI floorplanning with boundary constraints using a Corner Block List (CBL) representation. We identify the necessary and sufficient conditions of the CBL representation for the boundary constraints. We design a linear time approach to scan the conditions and formulate a penalty function to punish the constraint violation. A simulated annealing process is adopted to optimize the floorplan. Experiments on MCNC benchmarks show promising results.

In this paper, we present a design for an optical video transmission system employing a super wide-band FM modulation scheme. We focus on the design of optical transmitters and receivers, especially a wide-band electrical-to-optical converter and optical-to-electrical converter. With this system, it is important to develop optical and microwave devices which have a wide frequency response combined with flat group delay characteristics in order to improve the quality of the video signals after transmission. We also analyze theoretically the hybrid transmission capacity of AM analog video signals and 64QAM signals for digital video and data, and show the FM modulation parameters needed to realize high quality transmission. An experimental evaluation shows that our designed optical transmitter and receiver achieve high quality for the various channel plans for AM/64QAM hybrid transmission. The system has high received optical sensitivity and a wide optical dynamic range, allowing it to distribute analog video, digital video, and Internet data to many users over a wide area.

This paper proposes an automatic dispersion equalization system using extracted clock power monitoring in order to facilitate the field installation of high-speed time-division multiplexed (TDM) systems over existing fiber cables. The proposed scheme adjusts the dispersion of a variable-dispersion equalizer so as to maximize the extracted clock power level. This scheme has a simple configuration, needs no communication channel between the transmitter and the receiver, and is sensitive to parameters such as initial chirping and fiber input power. The clock power dependence on the fiber dispersion is theoretically analyzed assuming that the return-to-zero (RZ) format is used and that pulse broadening is small compared to the bit duration. We show that the clock power is maximized when the dispersion-induced waveform distortion is minimized. Numerical simulations show that the proposed scheme is effective with the non-return-to-zero (NRZ) format and for the case that the optimum total dispersion deviates from zero due to initial and/or self-phase modulation (SPM)-induced chirping. The operation of the proposed automatic equalization system is experimentally confirmed in 20-Gbit/s transmission using both RZ and NRZ formats. Moreover, a 40-Gbit/s transmission experiment over 200 km of dispersion-shifted fiber (DSF) is successfully demonstrated using the proposed equalization scheme.

As LSIs are two-dimensional structures, the number of external pins increases at a lower rate than the corresponding increase in the number of gates on the LSI. Therefore, the number of flip-flops on a scan path increases as the density of gates on LSIs rises, resulting in longer test application times. In this paper, three novel DFT strategies aimed at reducing test application time are proposed. DFT strategy 1 is a full scan design method with test point insertion, DFT strategy 2 is a partial scan design method, and DFT strategy 3 is a partial scan design method with test point insertion. Experimental results show that these DFT strategies reduced the test application times by 45% to 82% compared with conventional full scan design methods.

This paper presents a new adaptive blind separation of sources (BSS) method for linear and non-linear mixtures. The sources are assumed to be statistically independent with non-uniform and symmetrical PDF. The algorithm is based on both simulated annealing and density estimation methods using a neural network. Considering the properties of the vectorial spaces of sources and mixtures, and using some linearization in the mixture space, the new method is derived. Finally, the main characteristics of the method are simplicity and the fast convergence experimentally validated by the separation of many kinds of signals, such as speech or biomedical data.

The present paper treats the analysis and design method of the (H)NRD guide and E-plane rectangular waveguide integrated structures on the basis of the transverse resonance technique. The analysis is made by assuming a resonant cavity short-circuited at appropriate reference planes and considering the cavity as a waveguide discontinuity problem in the transverse direction. The resonant lengths are determined from the transverse equivalent circuit, and the scattering parameters are calculated from the lengths. We analyze (H)NRD discontinuities and design two types of HNRD guide to E-plane waveguide transitions and a directional coupler composed of HNRD and E-plane waveguide. The theoretical results are in good agreement with results calculated by an EM-simulator.

This paper introduces a new digital ATC (Automatic Train Control device) system. In the current ATC, the central ATC logic device calculates permissive speed of each blocking section and controls speed of all trains. On the other hand, in the new digital ATC, the central logic controller calculates each position to which a train can move safely, and sends the information on positions to all trains. On each train, the on-board equipment calculates an appropriate braking pattern with the information, and controls velocity of the train. That is, in the new system, the device on each train autonomously calculates permissive speed of that train. These special features realize ideal speed control of each train making full use of its performance for acceleration and deceleration, which in turns allows high-density train operations.

Multisignature scheme realizes that plural users generate the signature on a message, and that the signature is verified. Various studies on multisignature have been proposed. They are classified into two types: RSA-based multisignature, and discrete logarithm problem (DLP) based multisignature, all of which assume that a message is fixed beforehand. In a sense, these schemes do not have a feature of message flexibility. Furthermore all schemes which satisfy with order verifiability designate order of signers beforehand. Therefore these protocols have a feature of order verifiability but not order flexibility. For a practical purpose of circulating messages soundly through Internet, a multisignature scheme with message flexibility, order flexibility and order verifiability should be required. However, unfortunately, all previous multisignature do not realize these features. In this paper, we propose a general model of multisignature schemes with flexibility and verifiability. We also present two practical schemes based on DLP based message recover signature and RSA signature, respectively.

It is necessary condition for digital watermarking method for embedding memos or index data into digital photograph and so on that anyone can extract embedded data without specific keys or secret information. In this paper, we propose a data hiding technique for embedding index data into color images using wavelet transform. The proposed method keeps image quality and robustness against JPEG compression and general image processing using quantitative relation of wavelet coefficients.

We report the process flow and technological features of Infineons' 75 GHz bipolar technology, which is characterized by a double-poly self-aligned transistor structure and a SiGe base, grown by selective epitaxy. The dependence of the epitaxial deposition on growth conditions and the influence of layout on the growth process is discussed, especially for different kinds of reticles: bipolar-ICs, BICMOS-ICs and discrete semiconductors. Finally, our monitoring concept for the control of the selective SiGe epitaxy is presented and compared with alternative methods of process control.

We present a 5.8 GHz VCO for the 5 GHz HIPERLAN/2 and U-NII band. The VCO uses a center-tapped inductor and a substrate shield to improve phase noise. Sensitivity to supply voltage and temperature is reduced by an amplitude control block. The design is based on a distributed inductor model which allows optimization without antecedent inductor measurements. The circuit is fabricated in a 0.8 µ m 45 GHz fT low-cost SiGe-HBT technology and operates with a supply voltage of -2.0 V to -3.3 V .

The low bias region of the base current has been studied in SiGe HBTs and shown to arise from tunneling at the emitter periphery. Tunneling also describes the reverse bias base-emitter current, which we believe is enhanced by mid-gap states. The reverse bias causes damage to the base-emitter region, increasing the base current. We also show that after a short period of severe reverse bias stress the base current displays random telegraph signals. These phenomena are often observed in silicon bipolar transistors, confirming that the incorporation of SiGe has not produced any other undesirable characteristics.

This paper presents an automatic synthesis method of active analog circuits that uses evolutionary search and employs some topological features of analog integrated circuits. Our system firstly generates a set of circuits at random, and then evolves their topologies and device sizing to fit an environment which is formed by the fitness function translated from the electrical specifications of the circuit. Therefore expert knowledge about circuit topologies and sizing are not needed. The capability of this method is demonstrated through experiments of automatic synthesis of CMOS operational amplifiers.

The current-voltage characteristics of InP-based HBTs with InAlAs-InP composite emitters have been measured as a function of the thickness of the InP layer in the emitter. As the thickness varies, characteristics such as the gain and the ideality factor vary qualitatively as expected from the changes in position of the InAlAs barrier in the emitter. Quantitatively, however, the variations indicate that the interfaces vary systematically with InP thickness, becoming more abrupt for emitters with thicker InP layers.

This paper compares the performance of SiGe and GaAs HBT power amplifiers for wireless handset applications. To make a fair comparison, we have designed and characterized monolithic SiGe power amplifiers and compared their performance with similarly designed commercial GaAs power amplifiers for both cellular dual-mode (CDMA/AMPS) and PCS CDMA handsets. The designed SiGe cellular power amplifier, at 824-849 MHz, satisfies both CDMA and AMPS requirements in output power, linearity and efficiency. At Vcc = 3 V, the power amplifier shows excellent linearity (1st ACPR < -44.1 dBc and 2nd ACPR < -57.1 dBc) up to 28 dBm for CDMA applications. Under the same bias conditions, the power amplifier also meets AMPS handset requirements in output power (up to 31 dBm) and linearity (with 2nd and 3rd harmonic to fundamental ratios lower than -37 dBc and -55 dBc, respectively). At the maximum output power level, the worst power-added-efficiencies (PAE) are measured to be 36% for CDMA and 49% for AMPS operations. The performance of SiGe cellular power amplifiers is comparable to that of GaAs HBT power amplifiers but with two exceptions: 1) SiGe power amplifier showed a relatively low gain than that of GaAs amplifiers (about 4-6 dB). This may be attributed to the use of low-Q inductors (Q < 5) for on-chip impedance matching, imprecise device modeling and the higher interconnect parasitics; 2) SiGe power amplifiers survived severe output mismatch (VSWR > 12:1) up to Vcc = 4 V but died instantly as Vcc > 4.5 V, due to their low breakdown voltages. We also observed inter-modulation spurs (-22 dBc) appeared in CDMA outputs at two specific tuning angles, but with no spurs appeared in AMPS outputs at any tuning angle. The possible mechanism for generating those output spurs will be discussed as well. In addition, We also designed and characterized a monolithic SiGe power amplifier for PCS (1850-1910 MHz) CDMA handset applications. At Vcc = 3.5 V, the SiGe PA satisfies the linearity requirement up to maximum power output 28 dBm with a comparable gain (23-26 dBm), but has a relatively low PAE ( 25%) compared with that of GaAs counterparts at the high output power end.

Silicon Germanium Heterostructure field effect transistors have been proposed as a promising extension to the CMOS technologies affording enhanced performance at relaxed geometries. Particularly promising is the potential of SiGe Heterostructure MOS and Heterostrucure FET at the low power operating regime. We discuss circuit design techniques applicable in the micropower regime which can be applied to SiGe HMOS technologies. We then review recent results in HMOS both from the material and the applications point of view. We conclude by reporting simulation results indicating the potential of SiGe HMOS in radiofrequency micropower applications.