Precise and quick multi-beam forming including null control will be one of the key technologies for the future satellite communication systems utilizing SDMA (Space Division Multiple Access) and DOA (Direction of Arrival) estimation. In order to realize the precise multi-beam forming, calibration procedure is indispensable since there are several unavoidable factors that degrade the multi-beam patterns of the array. Particularly amplitude and phase imbalance between RF circuits needs to be calibrated frequently and quickly when the array system exists in changeable environment since the imbalance easily occurs due to thermal characteristics of each RF circuit. This paper proposes a simple and high-speed remote calibration scheme compensating for amplitude and phase imbalance among RF circuits of a transmitting adaptive array antenna onboard satellite. This calibration is conducted at a remote station such as a gateway station on the ground in the satellite communication system, by utilizing the received signal including the temporally multiplexed orthogonal codes transmitted from the array antenna onboard satellite. Since the calibration factors for all the antenna elements can be simultaneously obtained by the parallel digital signal processing, calibration time can be drastically reduced. The accuracy of this calibration is estimated by simulation. Simulation results show that the amplitude imbalance among RF circuits can be suppressed within the range from -0.5 dB to +0.25 dB for the initial imbalance ranging from -2 dB to +3.5 dB, phase imbalance can be suppressed within the range of -3 deg. to +3 deg. for the initial imbalance ranging from -120 or +180 deg. by this method. The amplitude and phase deviations among the elements can be suppressed within 0.36 dB and 2.5 degrees, respectively, in 80% of probability. Simulation results also show that this calibration method is valid under the relatively bad carrier-to-noise conditions such as -10 dB at the receiver. Good improvement of the multi-beam patterns by this calibration is shown under the low carrier-to-noise ratio condition.

This paper describes an improved nonlinear GaAs FET model and its parameter extraction procedure for almost all operating conditions such as the small-signal condition, the power saturated condition, and the controlled-resistance condition. The model is capable of modeling the gate voltage dependent drain current and its derivatives in the saturated region as well as the drain voltage dependent drain current and its derivatives in the linear region. The model can take into account the frequency dispersion effects of both transconductance and output conductance. The model describes forward conduction and reverse conduction currents. Deriving the capacitance part of the model from unique charge equations satisfies charge conservation. The model accurately predicts voltage-dependent S-parameters, spurious response in an active condition and inter-modulation response in the controlled-resistance condition of a GaAs FET.

Currently, the most popular model in data compression theory is that of stationary ergodic sources. But there do exist sequences each of which is not emitted from any stationary ergodic source but can be compressed sufficiently by a certain algorithm. We estimate the size of the set of such sequences in terms of Hausdorff dimension.

An efficient large-signal modeling method of FET using load-line analysis is proposed, and it is applied to non-linear characterization of FET. In this method, instantaneous drain-source voltage Vds(t) and drain-source current Ids(t) waveforms are determined by load-line analysis while non-linear parameters in a large-signal equivalent circuit of FET are defined as the average values over one period corresponding to instantaneous Vds(t) and Ids(t). Output power (Pout), power added efficiency (ηadd), and phase deviation calculated by using such an equivalent circuit of FET agree well with the measured results at 933.5 MHz. Phase deviation mechanism is explained based on the large-signal equivalent circuit of FET, and it is shown how non-linear parameters, such as trans-conductance (gm), drain-source resistance (Rds), gate-source capacitance (Cgs), and gate leak resistance (Rig) contribute to positive or negative phase deviations. The difference between small-signal and large-signal S-parameters (S11, S12, S21, S22) is also discussed. The proposed large-signal modeling method is considered to be useful for the design of high power, high efficiency, and low distortion amplifiers as well as the investigation of the behavior of FET in large-signal operating conditions.

A large-signal simulation program for multi-stage power amplifier modules by using a novel interpolation is presented. This simulation program has the function to make the Load-Pull and Source-Pull (LP/SP) data required for the simulation. By using the interpolation, a lot of LP/SP data can be made from a small number of measured LP/SP data. The interpolation is based on the calculation method using a two-dimensional function. By using the simulation program, we can calculate the large-signal characteristics depended on frequency and temperature of the multi-stage amplifier module. We apply the simulation program to the design of the amplifier. The calculated and measured results agree well. The accuracy of the presented interpolation is confirmed. It is considered that the presented program is useful to calculate large-signal characteristics of the amplifier module.

This paper proposes a novel adaptive array configuration that reduces high-power co-channel interference (CCI) by utilizing the difference in arrival times between CCI and the desired signal in asynchronous TDD systems. The proposed adaptive array extracts only the CCI and employs pre-null steering for only the CCI by utilizing the fact that only the CCI arrives during the guard time in asynchronous TDD systems. Since the proposed adaptive array enables us to apply the Minimum Mean Square Error (MMSE) algorithm through synchronization with the desired signal using the output signal obtained by pre-null steering, high quality transmission can be achieved even in the presence of high-power CCI. Moreover, based on measurements using a fading simulator and field data, an adaptive array testbed exemplifying the proposed configuration is presented to show the reduction in the high-power CCI.

In this paper, we present a new transmit diversity scheme with power control by using two transmit antennas in which the power control unit is added to adaptively suit the channel fading variation. Compared to the transmit diversity scheme (STD, one space time coding scheme) proposed by Alamouti and the traditional maximal ratio combining (MRC) diversity scheme employed at the receiver, simulation results indicate that the new scheme has considerable performance gain. We also discuss the effects of the imperfect channel parameter estimation on the performance of the system. Simulation results show that the new system is more robust to the estimation error of channel fading parameters than the STD. As the signal to noise ratio is relatively high, the diversity scheme with power control is more sensitive to the channel estimation error compared to the MRC. But when the channel estimation accuracy is relatively high, the diversity scheme with power control still has better performance than the ideal MRC as the BER is about 1 10-3.

For on-chip matching Si-MMIC fabricated on a conventional low resistivity Si substrate, the loss of on-chip inductors is quite high due to the dielectric loss of the substrate. In order to reduce the loss of on-chip matching circuit, the use of high resistivity Si substrate is quite effective. By using electro-magnetic simulation, the relationship between coplanar waveguide (CPW) transmission line characteristics and the resistivity of Si substrate is discussed. Based on the simulated results, the resistivity of Si substrate is designed to achieve lower dielectric loss than conductor loss. The effectiveness of high resistivity Si substrate is evaluated by the extraction of equivalent circuit model parameters of the fabricated on-chip spiral inductors and the measurement of the fabricated on-chip matching Si-MMIC LNA's.

This letter presents a method which attempts to minimize the number of spill codes to resolve usage conflicts of distributed registers in application specific DSPs. It searches for a set of ordering restrictions among operations which sequentialize the lifetimes of the values residing in the same register as much as possible. Experimental results show that the proposed analysis method reduces the number of register spills into 28%.

A complex coefficient filter obtained by directly exchanging several reactance elements included in a real coefficient BPF for imaginary valued resistors is described. By using the proposed method, we obtain four varieties of complex coefficient filters. The stability problem is examined.

Magnetic random access memory (MRAM) possesses the attractive properties of non-volatility, radiation hardness, nondestructive readout, low voltage, high access speed, unlimited read and write endurance and high density. MRAM technology is described for the devices using giant magnetoresistance (GMR) and tunneling magnetoresistance (TMR) materials in this paper. The TMR type MRAM architectures using ferromagnetic tunneling junctions (MTJ) are more attractive for mainstream RAM applications than the GMR type, because the signal of the TMR type is larger than that of the GMR type. A MRAM device with an MTJ plus MOS transistor switch architecture, which can provide large signal-to noise ratio, is detailed. A design of the MTJ element is discussed and the requirements for the junction resistance and the TMR needed for the memory device are demonstrated based on the simple signal voltage calculations. The TMR significantly decreases with increasing bias voltage, which leads to the reduction of the signal voltage for the actual MRAM. A ferromagnetic double tunneling junction is proposed for the high density MRAM application demanding large signal voltage, because of the smaller degradation of the TMR for the bias voltage, compared with that of the conventional single junctions. Recent trials of MRAM fabrication are introduced, which demonstrates high-speed access time. Finally, challenges for the higher bit density MRAM above Gb are discussed, and it is noticed that higher signal voltage, lower power consumption for writing and novel cell designs are needed for the achievement.

The stage 3/2 decoding scheme, originally suggested by U. Timor, is modified for a Rayleigh fading channel to improve the performance of a fast frequency-hopped multiple access/multilevel frequency shift keying system. When signal-to-noise ratio per bit is 30 dB, the simulation results show that the modified stage 3/2 decoding scheme increases the spectral efficiency by 11% compared to the modified stage 1 decoding scheme at bit error rate of 10-3. Further, the performance comparisons are made between the modified multistage decoding scheme and the diversity combining methods, where the modified stage 3/2 decoding scheme shows better performance.

The inter-cell interference between uplinks and downlinks in CDMA packet communication systems, employing a shared-TDD scheme, is evaluated under cellular environments. It is found that interference between base stations rarely degrades uplink throughput, but interference between mobile stations substantially degrades downlink throughput. A transmission power control scheme is proposed to improve the downlink throughput. The proposed scheme increases the transmission power of downlink packets when they are re-transmitted, and thus, improves the signal-to-interference ratio of the downlink re-transmission packets. Computer simulation shows that this scheme increases downlink throughput without sacrificing the uplink throughput until the uplink throughput reaches a maximum value.

In this letter, performance evaluation of a system that combines between Code-Division Multiple Access (CDMA) and ALOHA protocol in multimedia networks is presented. In our analysis, we compare the performance between the two basic techniques of ALOHA protocol, i.e., Slotted-ALOHA (S-ALOHA) and Unslotted-ALOHA (U-ALOHA), when combined with CDMA scheme to support voice and data users operating in same CDMA channel. The quality of service (QoS) required for voice and data media is completely taken care of. We obtain the throughput of data media, and the outage probability for voice considering both voice and data offered loads. Throughput performance of S-ALOHA technique is almost twice of that of U-ALOHA. However, we show in this letter that when we combine CDMA with the two basic techniques of ALOHA to accomplish multimedia transmission, both techniques have almost same performance. And, thus, CDMA U-ALOHA can be a good candidate for multimedia networks.

In this paper, we survey the fairness issues in the congestion control mechanisms of TCP, which is one of most important service aspects in the current and future Internet. We first summarize the problems from a perspective of the fair service among connections. Several solution methods are next surveyed. Those are modifications of TCP congestion control mechanism and router support for achieving the fair service among TCP connections. We finally investigate the fair share of resources at endhosts.

This paper focuses on the comparison of OFDM system channel estimation using time domain techniques and using frequency domain techniques. The channel model is based on the Taiwan DTV field-testing results, with static and dynamic multipath distortion. The simulation results prove that the channel estimation performance of the OFDM system in the time domain is better than in the frequency domain.

In distributed network systems, it is one of the most important problems how to assign the files to servers in view of cost and delay. It is obvious that there is a trading-off relationship between costs and delays in these systems. In order to evaluate the optimization that the total cost is minimized subject to the total delay, we have presented the Optimal File Allocation Model as 0-1 integer programming, and have investigated the general characteristics in distributed systems. In this model, we have introduced many cost and delay parameters to evaluate the total cost and delay in the system more exactly. In constructing practical systems, it is necessary to investigate the weight and the contribution of each parameter to the total cost. It is very useful to show how to estimate cost and delay parameters on the basis of this analysis. In this paper, we analyze the sensitivity of these parameters and make clear the influence between principal parameters.

We demonstrate all-optical clock recovery at 160 Gbit/s by injection locking of a 10 GHz mode-locked laser diode. Effective locking in a range of 10 MHz is observed for average input powers around -10 dBm. The timing jitter is analyzed for data rates between 10 Gbit/s and 160 Gbit/s. Beyond 40 Gbit/s, the high frequency timing jitter of the slave laser becomes of prime importance and has to be taken into account since it degrades the performance of a subsequent receiver. Increasing power penalties are found, especially beyond 80 Gbit/s.

Epitaxial SrTiO3(STO) film on epitaxial (Ti,Al)N/Si(100) was successfully obtained using a Ti-buffer layer. The SrTiO3 film was (100) oriented and grew in parallel epitaxial relationship (cube-on-cube), i.e., (100)SrTiO3//(100)(Ti,Al)N//(100)Si, <110> SrTiO3//<110> (Ti,Al)N//<110> Si. The Ti-buffer layer was grown on (Ti,Al)N by magnetron sputtering, and the thickness of the buffer layer was 2-10 nm. After the STO film was sputtered, the Ti-buffer layer was changed to polycrystalline anatase-TiO2.

Our aim is to develop an intuitive sound designing interface for non-expert users. We propose editing sound by sound, which means using vocal mimicking as a "master" to transform the pitch and amplitude envelope. Our technique allows any user to easily and intuitively design sound because it requires no knowledge of acoustic features.