This paper presents a multimedia architecture extension design for a 200-MHz, 1.6-GOPS embedded RISC processor. The datapath architecture of the processor which realizes parallel execution of data transfer and SIMD (single instruction stream multiple data stream) parallel arithmetic operations is designed. Four SIMD parallel 16-bit MAC (multiply-accumulation) instructions are introduced with a symmetric rounding scheme which maximizes the accuracy of the 16-bit accumulation. This parallel 16-bit MAC on a 64-bit datapath is shown to be efficiently utilized for DSP applications such as the correlation and the matrix-vector multiplications in the multimedia RISC processor. By using the parallel MAC instruction with the symmetric rounding scheme, a 2D-IDCT which satisfies the IEEE1180 can be implemented in 202 cycles.

This paper proposes a design method of variable IIR digital filters based on balanced realizations and minimum round-off noise realizations of digital filters. Highly accurate variable digital filters are easily derived by the proposed method. The coefficient matrices of both realizations of second-order digital filters are obtained directly from prototype realizations. The filter coefficients of variable digital filters can be obtained by frequency transformations to the realizations. The filter coefficients are presented as truncated Taylor series for the purpose of reducing a number of calculations to tune the coefficients. However the proposed filters have highly accurate variable characteristics against the coefficient truncation since balanced realizations and minimum round-off noise realizations have very low coefficient sensitivities, which are invariant under the frequency transformations. Moreover, the dynamic ranges of the proposed filters are almost constant against the frequency transformations. Numerical examples show the effectiveness of the variable digital filters designed by the proposed method.

The adaptive system design by 16-bit fixed point processing enables to employ an inexpensive digital signal processor (DSP). The narrow dynamic range of such 16 bits, however, does not guarantee the same performance that is confirmed beforehand by computer simulations. A cause of degrading the performance originates in the operation halving the word length doubled by multiplication. This operation rounds off small signals staying in the lower half of the doubled word length to zero. This problem can be solved by limiting the multiplier to only its sign () like the signed regressor algorithm, named 'bi-quantized-x' algorithm in this paper, for the convenience mentioned below. This paper first derives the equation describing the convergence property provided by a type of signed regressor algorithms, the bi-quantized-x normalized least mean square (NLMS) algorithm, and then formulates its convergence condition and the step size maximizing the convergence rate. This paper second presents a technique to improve the convergence property. The bi-qiantized-x NLMS algorithm quantizes the reference signal to 1 according to the sign of the reference signal, whereas the technique moreover assigns zero to the reference signal whose amplitude is less than a predetermined level. This paper explains the principle that the 'tri-qunatized-x' NLMS algorithm employing the technique can improve the convergence property, and confirms the improvement effect by computer simulations.

In this paper we propose a close-loop queueing model of MPLS switch under different label-setup and release policies, supporting both traffic-driven and topology-driven connection setup procedures. This model can emulate the behavior of TCP under the MPLS switch when the maximum window size is sustained and the packet loss rate is negligible. From the proposed flow-based MPLS switch model, one can clearly observe the competition of multiple IP flow for limited number of labels, and how the label-setup policy and the label-release policy affect the system performance. We find that Norton's theorem can be applied to solve this sophisticated queueing model. Therefore, with very limited computational complexity with respect to the number of IP flows or labels, the proposed mathematical model and the approximation of label competition can be used to obtain the desired performance metrics, such as the throughput, the label-setup rate, and the channel utilization. Finally, the trade-off among performance metrics can be observed as well.

Detection of nonlinearly distorted signals is an essential problem in telecommunications. Recently, neural network combined conventional equalizer has been used to improve the performance especially in compensating for nonlinear distortions. In this paper, the self-organizing map (SOM) combined with the conventional symbol-by-symbol detector is used as an adaptive detector after the output of the decision feedback equalizer (DFE), which updates the decision levels to follow up the nonlinear distortions. In the proposed scheme, we use the box distance to define the neighborhood of the winning neuron of the SOM algorithm. The error performance has been investigated in both 16 QAM and 64 QAM systems with nonlinear distortions. Simulation results have shown that the system performance is remarkably improved by using SOM detector compared with the conventional DFE scheme.

Digital signal processors (DSPs) usually employ indirect addressing using address registers (ARs) to indicate their memory addresses, which often introduces overhead codes in AR updates for next memory accesses. Reduction of such overhead code is one of the important issues in automatic generation of highly-efficient DSP codes. In this paper, a new automatic address allocation method incorpolated with computational order rearrangement at local commutative parts is proposed. The method formulates a given memory access sequence by a graph representation, where several strategies to handle freedom in memory access orders at the computational commutative parts are introduced and examined. A compiler scheme is also extended such that computational order at the commutative parts is rearranged according to the derived memory allocation. The proposed methods are applied to an existing DSP compiler for µPD77230(NEC), and codes generated for several examples are compared with memory allocations by the conventional methods.

The diverse broadcast means that will be available in the future will cause an increased demand for programs. When the input of the posture of an agent is used to manipulate a virtual computer graphics actor, it is better if the system does not require a special studio and devices. In the present paper, we propose a way to extract images from a single picture based on estimates of blooming. This is done using a partial auto-correlation analysis that carries out backward and forward predictions simultaneously. And, we divide targets into the stratified depth from a single image. An experiment was conducted using a picture taken with a digital camera, and satisfactory results were obtained.

A unified polyphase representation of analysis and synthesis filter banks is introduced in this paper, and then the efficient implementation on digital signal processors (DSP) is investigated. Especially, the number of memory accesses, power consumption, processing accuracy and the required instruction cycles are discussed. Firstly, a unified representation is given, and then two types of procedures, SIMO system-based and MISO system-based procedures, are shown, where SIMO and MISO are abbreviations for single-input/multiple-output and multiple-input/single-output, respectively. These procedures are compared to each other. It is shown that the number of data load in SIMO system-based procedure is a half of that in MISO system-based procedure for two-channel filter banks. The implementation of M-channel filter banks is also discussed.

We have proposed area-reduction techniques for superscalar datapath architectures with 34 SIMD instructions and have developed an integer-media unit based on these techniques. The unit's design is both functionally asymmetrical and integer-SIMD unified, and the resulting savings in area are 27%-48% as compared to other, functionally equivalent mid-level microprocessor designs, with performance that is, at most, only 7.2% lower. Further, in 2-D IDCT processing, the unit outperforms embedded microprocessor designs without SIMD functions by 49%-118%. Specifically, effective area reduction of adders, shifters, and multiply-and-adders has been achieved by using the unified design. These area-effective techniques are useful for embedded microprocessors and scalable systems that employ highly parallel superscalar and on-chip parallel architectures. The integer-media unit has been implemented in an evaluation chip fabricated with 0.15-µm 5-metal CMOS technology.

An effective way to realize scaled CMOS with both requirements of high current drive and low supply voltage is to introduce high mobility channel such as strained Si. This paper proposes a new device structure using the strained-Si channel, strained-Si-on-Insulator (strained-SOI) MOSFET, applicable to sub-100 nm Si CMOS technology nodes. The device structure and the advantages of strained-SOI MOSFETs are presented. It is demonstrated that strained-SOI MOSFETs are successfully fabricated by combining SIMOX technology with re-growth of strained Si and that n- and p-MOSFETs have mobility of 1.6 and 1.3 times higher than the universal one, respectively. Furthermore, it is also shown that ultra-thin SiGe-on-Insulator (SGOI) virtual substrates with higher Ge content, necessary to further increase mobility and to realize fully-depleted SOI MOSFETs, can be made by oxidation of SGOI structure with lower Ge content.

A lot of efforts have been made to develop the international Internet environment. In order to achieve a better and efficient information infrastructure around the globe, there are very strong urgent demands in the area of Asia and Pacific for a practical working environment where engineers and researchers in related fields work cooperatively. Our AI3 Project was started in 1995 by WIDE Project and JSAT. It has been operating a satellite based testbed network in Southeast Asia and conducting a series of research activities using the testbed. In this paper, we explain AI3 satellite Internet infrastructure and describe our efforts of the deployment in Asia using our developed technology. Furthermore, we evaluate our testbed network from the aspect of sustainable international collaboration.

In [3], the decision feedback channel estimation (DFCE) for M-ary orthogonal modulation in direct sequence/code division multiple access (DS/CDMA) systems was proposed. However, the performance of the DFCE in the multiuser environment is severely degraded due to multiple access interference (MAI). In this letter, to overcome this problem, we modify the DFCE as multistage configurations using a multistage parallel interference cancellation (PIC) scheme. According to the results of our simulations, the performance of coherent demodulation using the proposed multistage DFCE is significantly improved in comparison with conventional demodulation in [3].

The design and implementation of a novel English writing environment is described. The system integrates modern computer and networking technologies with analytical tools from linguistics and language pedagogy to construct an advanced English writing environment. The system is not only suitable for students in learning English, but also of benefit to teachers in making comments and detecting learners' common difficulties. Furthermore, the collected essays from students and comments from teachers constitute a useful learner corpus. This is also of benefit to researchers in analyzing learners' persistent errors. In order to allow global access from the Internet, the system is web-based. Users, for example, students, teachers, and researchers, may access the system through web browsers. The system was developed in a cooperative effort of Computers And Networking (CAN) laboratory and the Research in English Acquisition and Pedagogy (REAP) Group at Tamkang University. The system has been piloted by six English faculty members at Tamkang University and is currently being used in five high schools in Taiwan. The learner corpus currently consists of over 800,000 word tokens of learners' writing.

In this paper, a novel beam selection transmit diversity (BSTD) scheme is proposed for the downlink transmission of frequency division duplex (FDD) based DS-CDMA system. As a combination of selection transmit diversity and steering vector based beamforming, the BSTD scheme provides diversity gain as well as reducing multiple access interference in downlink. Moreover, to have a better understanding, the performance of the BSTD is also compared with other schemes. The comparison results show that the BSTD would be a promising candidate for the downlink transmission if both performance and implementation complexity are considered.

This paper describes a method of age-group classification of young males based on their facial images. The facial shapes of males and females are mostly formed by age 20 and 15, respectively. Our study only considered young males as they have a longer period during which facial shape is a determining factor in age estimation. Age classification was carried out using artificial neural networks. We employed 440 facial images in our experiment, composed of 4 different photographic images taken at ages 12, 15, 18 and 22 of 110 young males. Two methods of age classification were used, each employing different features extracted from the facial images, namely, "mosaic features" and "KL features. " As a result, we obtained about an 80% successful classification rate using mosaic features, and a slightly lower rate using KL features. We also analyzed the connection weights between the hidden and input layers of the trained networks, and examined facial features characteristic to each age group.

In this paper, an attempt was made to evaluate mental workload using chaotic analysis of EEG. EEG signals registered from Fz and Cz during a mental task (mental addition) were recorded and analyzed using attractor plots, fractal dimensions, and Lyapunov exponents in order to clarify chaotic dynamics and to investigate whether mental workload can be assessed using these chaotic measures. The largest Lyapunov exponent for all experimental conditions took positive values, which indicated chaotic dynamics in the EEG signals. However, we could not evaluate mental workload using the largest Lyapunov exponent or attractor plot. The fractal dimension, on the other hand, tended to increase with the work level. We concluded that the fractal dimension might be used to evaluate a mental state, especially a mental workload induced by mental task loading.

This paper discusses recognition up to intensities of mix of primary facial expressions in real time. The proposed recognition method is compatible with the MPEG-4 high level expression Facial Animation Parameter (FAP). In our method, the whole facial image is considered as a single pattern without any block segmentation. As model features, an expression vector, viz. low global frequency coefficient (DCT) changes relative to neutral facial image of a person is used. These features are robust and good enough to deal with real time processing. To construct a person specific model, apex images of primary facial expression categories are utilized as references. Personal facial expression space (PFES) is constructed by using multidimensional scaling. PFES with its generalization capability maps an unknown input image relative to known reference images. As PFES possesses linear mapping characteristics, MPEG-4 high level expression FAP can be easily calculated by the location of the input face on PFES. Also, temporal variations of facial expressions can be seen on PFES as trajectories. Experimental results are shown to demonstrate the effectiveness of the proposed method.

The Tropical Rainfall Measuring Mission (TRMM) is a United States-Japan joint project to measure rainfall from space. The first spaceborne rain radar is aboard the TRMM satellite. Rain/no-rain discrimination for the TRMM provides useful information for on-line data processing, storage, and post-processing analysis. In this paper, rain/no-rain discrimination for the TRMM has been validated through simulation and theory for the no-rain condition and by comparison with the ground-based radar data for rain conditions.

Si single-electron transistors with a high voltage gain at a considerably high temperature have been fabricated by vertical pattern-dependent oxidation. The method enables the automatic formation of very small tunnel junctions having capacitances of less than 1 aF. In addition, the use of a thin (a few ten nanometers thick) gate oxide allows a strong coupling of the island to the gate, which results in a gate capacitance larger than the junction capacitances. It is demonstrated at 27 K that an inverting voltage gain, which is governed by the ratio of the gate capacitance to the drain tunnel capacitance, exceeds 3 under constant drain current conditions.

The power consumption of hybrid logic circuits of single-electron transistors (SETs) and complementary metal-oxide-semiconductor field-effect transistors (CMOSFETs) was calculated. The SET/CMOS hybrid logic circuits consisted of SET logic trees and CMOS amplifiers, whose inputs were connected to the outputs of the SET logic trees, and it was shown that the reduction of interconnect capacitance between the inputs of CMOS amplifiers and the outputs of SET logic trees was essential to reduce the power consumption. In order to reduce the inter-connect capacitance, a new strategy of constructing logic trees with SETs and their complementary SETs both working as pull-down devices was proposed, for the first time. Consequently, a large amount of the interconnect capacitance could be eliminated and the power consumption of SET/CMOS hybrids was considerably lowered.