This paper discusses the features of SOI/CMOS circuits in comparison with bulk/CMOS circuits. We have to design circuits with small fan outs and short wires to take advantage of high-speed and low-power SOI/CMOS devices to their fullest. We can take advantage of the SOI/CMOS structure if the ratio of the source/drain capacitances to the gate capacitances is much greater in the load capacitance. Thus, we propose a new flip-flop circuit with a smaller gate capacitance. The flip-flop circuit operates 30% faster than the previous circuit at 2.0 V. We also propose a buffer circuit having less delay disparity between the complementary output signals. The buffer circuit has the delay disparity of 18 ps at 0.2 pF and 2.0 V. We fabricated an 8-bit frequency divider and a 4-bit demultiplexer using the proposed circuits and 0.35 µm SOI/CMOS process. The 8-bit frequency divider and the 4-bit demultiplexer operate at 2.8 GHz and 1.6 GHz, respectively, at 2.0 V.

This paper presents the evaluation for personal communication systems (PCS). Two types of PCS are supposed for low and high degree of mobility. The service area with 30km radius is covered by a multiple hexagonal cells, which are micro cells and macro cells for the low mobility and high mobility planes respectively. As for a traffic distribution, uniform and exponentially tapered traffic distributions are assumed. After defining the system model, cost evaluation form along with capacity has been derived. The evaluation and discussions are made in terms of cost economy, capacity and spectrum usage in various conditions. It is shown that there exist the optimum cell radius for the prescribed subscriber numbers and the integration of two systems is desirable for the support of full mobility with cost-effectiveness and spectrum efficiency.

This paper investigates the error rate performance of parallel combinatorial spread spectrum (PC/SS) communicaion systems that use coherent and differential multiphase modulation: multiphase parallel combinatorial spread spectrum (MPC/SS) communication systems. The PC/SS systems are multicode SS systems based on orthogonal pseudo-noise (PN) sequences. Data is transmitted by delivering a combination of multiple PN sequences among a set of pre-assigned PN sequences. In the MPC/SS systems, every PN sequence on transmission is modulated by q-ary coherent or differential phase shift keying (PSK). Symbol error rate (SER) and average bit error rate (BER) in coherent and differential MPC/SS systems are investigated. The BER comparison between the MPC/SS systems and simple multicode SS systems with q-ary coherent and differential PSK is also presented. Numerical results show that the MPC/SS systems are superior to the conventional q-ary PSK systems, if they have equal spectral efficiency.

An advanced intelligent network (IN) provides service management along with telecommunication services, and has a two-layer architecture, i.e., a transmission layer and an intelligent layer. An advanced IN's programmability is achieved by a service-independent platform of nodes in the intelligent layer, and service-dependent software called logic programs. In contrast to telecommunication services, models for service management have not yet been established. This paper presents both execution and specification models for service management. The execution model is composed of three hierarchies that apply to various kinds of management operation. The specification model has the capability to define the details of data items. The specification language for service management is also proposed. Simulation on dynamic SQL based DBMS solved that; (1) Logic programs for service management can be made small size on the model, and (2) To provide efficient database operation, programmability must be enhanced if service management includes table with variable number of field operation.

This paper presents a discrete-time multiple short-time Fourier transform (MSTFT) suitable for a time-frequency analysis and synthesis of discrete-time nonstationary signals. An overcomplete set of multiple windows in used for a frame constitution in l2 (Z) so that higher quality signal analysis and perfect reconstruction of the signal are achieved. A design method for a prototype window is given where the window can satisfy regularity condition and have a flexible, good time and frequency characteristic under constraint of the uncertainty principle. A dual frame is constructed using the prototype windows in the framework of a frame operator method. Efficient implementation structures for the MSTFT and its inverse transform appropriate for real time numerical processing is presented. Simulation results are given to illustrate the effectiveness for design of the MSTFT. The performance advantages as a new signal analysis tool are demonstrated with an experimental signal.

In this paper, a systematic method which generates the micro-architecture of Application Specific Instruction Processor (ASIP) is proposed. Different from previous works, the data path and control path are generated from the instruction sequence which is generated by translating the compiled assembly code. A graphical representation method called Register Transfer Graph (RTG) is introduced to describe the micro-operations of instruction sequence. To achieve high performance, we perform micro-operation level scheduling which dynamically assigns the micro-operations of instruction sequence to the control steps. By transforming the architecture using synthesis parameters, design space is explored more extensively. Connection cost is minimized by removing the inefficient data transfer paths.

In this paper we describe a method, which allows the likelihood normalization technique, widely used for speaker verification, to be implemented in a text-independent speaker identification system. The essence of this method is to apply likelihood normalization at frame level instead of, as it is usually done, at utterance level. Every frame of the test utterance is inputed to all the reference models in parallel. In this procedure, for each frame, likelihoods from all the models are available, hence they can be normalized at every frame. A special kind of likelihood normalization, called Weighting Models Rank, is also experimented. We have implemented these techniques in speaker identification system based on VQ-distortion codebooks or Gaussian Mixture Models. Evaluation results showed that the frame level likelihood normalization technique gives higher speaker identification rates than the standard accumulated likelihood approach.

The defects in the cold rolled strips have textural characteristics, which are nonuniform due to its irregularities and deformities in geometrical appearance. In order to handle the textural characteristics of images with defects, this paper proposes a surface inspection method based on textural feature extraction using the wavelet transform. The wavelet transform is employed to extract local features from textural images with defects both in the frequency and in the spatial domain. To extract features effectively, an adaptive wavelet packet scheme is developed, in which the optimum number of features are produced automatically through subband coding gain. The energies for all subbands of the optimal quadtree of the adaptive wavelet packet algorithm and four entropy features in the level one LL subband, which correspond to the local features in the spatial domain, are extracted. A neural network is used to classify the defects of these features. Experiments with real image data show good training and generalization performances of the proposed method.

This paper presents Super-CMOS SRAM process technology that integrates bipolar and CMOS transistors in a chip while adding only one ion implantation step and no lithography mask steps to the conventional CMOS SRAM process. The Super-CMOS SRAM process therefore has the same process cost as the CMOS SRAMs, while it achieves higher access speeds. In order to demonstrate the Super-CMOS SRAM, we have developed a 3.3 V/5 V 256 kb SRAM using 0.4 µm Super-CMOS process technology. By applying bipolar transistors to the sense amplifier circuits, a high-speed access time of 5.8 ns with a 3.0 V power supply is successfully achieved.

A 167-MHz 1-Mbit CMOS synchronous cache SRAM was developed using 0.40-µm process technology. The floor plan was designed so that the address registers are located in the center of the chip, and high-speed circuits were developed such as the quasi latch (QL) sense amplifier and the one-shot control (OSC) output register. To maintain suitable setup and hold time margins, an equivalent margin (EM) design method was developed. 167-MHz operation was measured at a supply voltage of 2.5 V and an ambient temperature of 75. The same margins 1.1 ns of the setup time and hold time were measured for the specifications of a setup time of 2.0 ns and a hold time of 0.5 ns.

We propose low Rayleigh scattering Na2O-MgO-SiO2 (NMS) glass as a candidate material for low-loss optical fibers. This glass exhibits Rayleigh scattering which is only 0.4 times that of silica glass, and a theoretical evaluation suggests that it is dominated by density fluctuation. An investigation of the optical properties of NMS glass reveals that a minimum loss of 0.06 dB/km is expected at a wavelength of 1.6 µm and that the zero-material dispersion wavelength is found in the 1.5 µm band. To establish the waveguide structure, we evaluated the feasibility of using F-doped NMS (NMS-F) glass as a cladding layer for an NMS core and found that it is suitable because it exhibits low relative scattering (e.g. 0.7) and is versatile in terms of viscosity matching. We also describe an attempt to draw optical fibers using the double crucible technique.

Signal Transition Graphs (STG's) are Petri nets, which were introduced to represent a behavior of asynchronous circuits. To derive logic functions from an STG, the reachability graph should be constructed. In the verification of STG's some method based on an Occurrence net (OCN) and its prefix, called an unfolding, has been proposed. OCN's can represent both causality and concurrency between two nodes by net structure. In this paper, we propose a method to derive a logic function by generating sub state space of a given STG using the structural properties of OCN.

Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) it (1) generates another PN or STG which is simpler than the original description and (2) produces an optimized net-list of an asynchronous controller in the target gate library while preserving the specified input-output behavior. An ability of back-annotating to the specification level helps the designer to control the design process. For transforming a specification petrify performs a token flow analysis of the initial PN and produces a transition system (TS). In the initial TS, all transitions with the same label are considered as one event. The TS is then transformed and transitions relabeled to fulfill the conditions required to obtain a safe irredundant PN. For synthesis of an asynchronous circuit petrify performs state assignment by solving the Complete State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial specification. The tool has been used for synthesis of PNs and PNs composition, synthesis and re-synthesis of asynchronous controllers and can be also applied in areas related with the analysis of concurrent programs. This paper provides an overview of petrify and the theory behind its main functions.

A 2.4 GHz band direct sequence (DS) spread spectrum (SS) radio frequency modem with a wide bandwidth of 26 MHz in half-duplex system has been newly developed using the small size (832 mm) and highly-efficient (-57 dBm) elastic type of surface acoustic wave (SAW) convolver. The size of SS modem is 905011 mm and the weight is 75 g. The power consumption of SS modem is 1.5 W and data rate is 206 kbps with 63 chips of PN code. Electrical characteristics measurements were made to evaluate the SS modem performance.

In this paper, we give a concrete example of a 10-bit video rate ADC and introduce the effect of top-down design methodology with analog-HDL from the viewpoint of utilization techniques. First, we explain that analog top-down design methodology can improve chip performance by optimizing the architecture. Next, we concretely discuss the importance of modeling and verification. Verification of the full system does not require extracting all the information for each block at the transistor level in detail. The flexible verification method that we propose can provide good and fast full chip verification. We think analog top-down disign methodology will become increasingly more important from now on because "system-on-chip" requires one chip mixed-signal system LSIs.

A 0.35 µm CMOS process for low-voltage, high-performance applications implemented in an ultra-thin-film SIMOX wafer: Shallow SIMOX, is described. Fully Depleted CMOS devices are realized in a 50 nm thick top Si film. Stable high speed, low-Vth transistors for low-voltage operation were developed by integrating a salicided dual gate process. Short-channel effects are suppressed by a novel channel-drain profile engineering. Low power consumption is achieved by the reduced diffusion capacitance of the SIMOX device and a thick, CMP planarized, intermetal dielectric to reduce metal interconnect capacitance's. Compared with the Bulk-Si CMOS devices, a factor of 1/5 reduction on power dissipation is achieved with this technology. A high ESD strength of 4 kV (HBM) demonstrates the applicability of this technology in advanced high-performance products.

This paper proposes a synthesis method to obtain speed-independent asynchronous circuits directly from signal transition graph (STG) specifications with single cycle signals which can be non-persistent and have free-choice operations. The resulting circuits are implemented with basic gates and asynchronous latches, and operate correctly under finite but unbounded gate delays and the zero wire delay assumptions. The proposed method introduces 5 types of lock relations to implement a non-persistent STG. A non-persistent STG can be implemented if every non-persistent signal to a signal t is super-locked with t. The resulting circuits are optimized by extracting of literals, mapping onto asymmetric C-elements, etc. Experimental results show that the proposed synthesis method outperforms the existing synthesis systems such as SYN and SIS.

A high-speed silicon-on-insulator (SOI) of a 1/8 frequency divider and a 64-bit adder were realized using an optimized gate-overlapped LDD and a self-aligned titanium silicide (TiSi2) source-drain structure. The advantages of the delay time and power consumption were analyzed by circuit simulation. The maximum operation frequency of the SOI divider is 2.9 GHz at 3.3 V. The SOI divider operates about 1.6 times faster than the bulk-Si divider. The power consumption of the SOI divider at the maximum operating frequency is about 60% of that of the bulk divider. On the other hand, the speed of the SOI adder is 1.9 nsec at 3.3 V. The SOI adder speed is about 1.3 times faster than the bulk adder. The power consumption of the SOI adder is about 80% of that of the bulk divider. It was found that the high speed, low power features of the SOI divider were due to the pass transistor which had low junction capacitance and little substrate bias effects, in addition to the low wiring capacitance and low fanout capacitance compared to the bulk adder. As a result, it is suggested that SOI circuits using pass transistor have a potential for GHz level systems and it is expected they will be applied to handy communication systems and portable computers used in the multimedia era.

The key circuit technologies for future giga-bit/low voltage operating high performance SOI-DRAM is described. Emphasis is made especially on the considerations for ways to overcome floating-body effects in order to obtain very long static/dynamic data retention time. A new scheme called a super body synchronous sensing scheme is proposed for low voltage operation at 1 V.

Resonance characteristics of a coupled dielectric resonator which consists of a Whispering Gallery mode dielectric disk resonator and a ring resonator located eccentrically are analyzed. New analytical results of resonance characteristic based on the distributed coupling phenomena between the disk and the ring are obtained. The resonance performances have also been verified experimentally on X band model. We have found that Free Spectral Range of the coupled resonator is several times larger than that of the single disk resonator and the single ring resonator, respectively. As a result, the eccentric coupled resonator discussed in this paper can be used as a frequency selective element in millimeter wave integrated circuits.