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20961-20980hit(21534hit)

  • A Recycling Scheme for Layout Patterns Used in an Old Fabrication Technology

    Yuji SHIGEHIRO  Isao SHIRAKAWA  

     
    PAPER-Algorithms for VLSI Design

      Vol:
    E76-A No:6
      Page(s):
    886-893

    When a new fabrication process is set up, especially in layout design for functional cells, of practical importance is how to make the best use of layout resources so far accumulated in old fabrication processes. Usually layout data of each element are expressed mostly in terms of positional coordinate values, and hence it is extremely tedious to modify them at every change of design rules for a new fabrication technology. To cope with this difficulty, the present paper describes an automatic recycling scheme for layout resources accumulated dedicatedly for functional cell generation. The main subject of this scheme is to transform given layout data into a layout description format expressed in layout parameters. Once layout data are parameterized, layout patterns of functional cells can be reconstructed simply by tuning up parameters in accordance with a new set of design rules. A part of implementation results are also shown.

  • Error Probability Analysis in Reduced State Viterbi Decoding

    Carlos VALDEZ  Hiroyuki FUJIWARA  Ikuo OKA  Hirosuke YAMAMOTO  

     
    PAPER-Communication Theory

      Vol:
    E76-B No:6
      Page(s):
    667-676

    The performance evaluation by analysis of systems employing Reduced State Viterbi decoding is addressed. This type of decoding is characterized by an inherent error propagation effect, which yields a difficulty in the error probability analysis, and has been usually neglected in the literature. By modifying the Full State trellis diagram, we derive for Reduced State schemes, new transfer function bounds with the effects of error propagation. Both the Chernoff and the tight upper bound are applied to the transfer function in order to obtain the bit error probability upper bound. Furthermore, and in order to get a tighter bound for Reduced State decoding schemes with parallel transitions, the pairwise probability of the two sequences involved in an error event is upper bounded, and then the branch metric of a sequence taken from that bound is associated with a truncated instead of complete Gaussian noise probability density function. To support the analysis, particular assessment is done for a Trellis Coded Modulation scheme.

  • Unified Scheduling of High Performance Parallel VLSI Processors for Robotics

    Bumchul KIM  Michitaka KAMEYAMA  Tatsuo HIGUCHI  

     
    PAPER-Parallel Processor Scheduling

      Vol:
    E76-A No:6
      Page(s):
    904-910

    The performance of processing elements can be improved by the progress of VLSI circuit technology, while the communication overhead can not be negligible in parallel processing system. This paper presents a unified scheduling that allocates tasks having different task processing times in multiple processing elements. The objective function is formulated to measure communication time between processing elements. By employing constraint conditions, the scheduling efficiently generates an optimal solution using an integer programming so that minimum communication time can be achieved. We also propose a VLSI processor for robotics whose latency is very small. In the VLSI processor, the data transfer between two processing elements can be done very quickly, so that the communication cycle time is greatly reduced.

  • CNV Based Intermedia Synchronization Mechanism under High Speed Communication Environment

    Chan-Hyun YOUN  Yoshiaki NEMOTO  Shoichi NOGUCHI  

     
    PAPER-Communication Networks and Service

      Vol:
    E76-B No:6
      Page(s):
    634-645

    In this paper, we discuss to the intermedia synchronization problems for high speed multimedia communication. Especially, we described how software synchronization can be operated, and estimated the skew bound in CNV when considering the network delay. And we applied CNV to the intermedia synchronization and a hybrid model (HSM) is proposed. Furthermore, we used the statistical approach to evaluate the performance of the synchronization mechanisms. The results of performance evaluation show that HSM has good performance in the probability of estimation error.

  • A Database-Domain Hierarchy-Based Technique for Handling Unknown Terms in Natural Language Database Query Interfaces

    Zouheir TRABELSI  Yoshiyuki KOTANI  Nobuo TAKIGUCHI  Hirohiko NISHIMURA  

     
    PAPER-Databases

      Vol:
    E76-D No:6
      Page(s):
    668-679

    In using a natural language database interface (NLI) to access the contents of a databese, the user queries may contain terms that do not appear at all in both the NLI lexicon and the database. A friendly NLI should not reject user queries with unknown terms, but should be able to handle them, and should be able to learn new lexical items. Such capability increases the usefulness of the NLI, and allows the NLI to more cover the domain of the underlying database. Therefore, a technique to handle unknown terms is decisive in designing a friendly NLI. In this work, we discuss a method that would allow a NLI to identify the meanings of unknown database field values, and terms that are exceeding the conceptual coverage of the database, in the user queries, by engaging the user in clarification dialogues based on a database-domain hierarchy. It will be shown that the method enables the NLI lexicon to learn new lexical items at run time while the clarification dialogues, and it may provide the necessary information for generating informative answers to some particular failing user queries. Moreover, the method is an efficient means to handle queries with insufficience contextual cues. The examples throughout this work are drawn from FIFA 90, an experimental NLI to a soccer database.

  • Nondeterminism, Bi-immunity and Almost-Everywhere Complexity

    John G. GESKE  

     
    PAPER-Algorithm and Computational Complexity

      Vol:
    E76-D No:6
      Page(s):
    641-645

    The main result of this paper is an almost-everywhere hierarchy theorem for nondeterministic space that is as tight as the well-known infinitely-often hierarchy theorems for deterministic and nondeterministic space. In addition, we show that the complexity-theoretic notion of almost-everywhere complex functions is identical to the recursion-theoretic notion of bi-immune sets in the nondeterministic space domain. Finally, we investigate bi-immunity in nondeterministic and alternating time complexity classes and derive a similar hierarchy result for alternating time.

  • Parallel Viterbi Decoding Implementation by Multi-Microprocessors

    Hui ZHAO  Xiaokang YUAN  Toru SATO  Iwane KIMURA  

     
    PAPER-Communication Theory

      Vol:
    E76-B No:6
      Page(s):
    658-666

    The Viterbi algorithm is a well-established technique for channel and source decoding in high performance digital communication systems. However, excessive time consumption makes it difficult to design an efficient high-speed decoder for practical application. This paper describes the implementation of parallel Viterbi algorithm by multi-microprocessors. Internal computations are performed in a parallel fashion. The use of microprocessors allows low-cost implementation with moderate complexity. The software and hardware implementations of the Viterbi algorithm on parallel multi-microprocessors for real-time decoding are presented. The implemented method is based on a combination of forming a set of tables and calculations. For efficient operation under fully parallel Viterbi decoding by microprocessors, we considered: (1) branch metrics processing, path metrics updating, path memory updating and decoding output for microprocessor, (2) efficient decomposition of the sequential Viterbi algorithm into parallel algorithms, (3) minimization of the communication among the microprocessors. The practical solutions for the problems of synchronization among the miroprocessors, interconnection network for communication among the microprocessors and memory management are discussed. Furthermore the performance and the speed of the parallel Viterbi decoding are given. For a fixed processing speed of given hardwares, parallel Viterbi decoding allows a linear speed up in the throughput rate with a linear increase in hardware complexity.

  • Toward the New Era of Visual Communication

    Masahide KANEKO  Fumio KISHINO  Kazunori SHIMAMURA  Hiroshi HARASHIMA  

     
    INVITED PAPER

      Vol:
    E76-B No:6
      Page(s):
    577-591

    Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

  • A Method for Contract Design and Delegation in Object Behavior Modeling

    Hirotaka SAKAI  

     
    PAPER-Software Theory

      Vol:
    E76-D No:6
      Page(s):
    646-655

    Behavior modeling of objects is critical in object-oriented design. In particular, it is essential to preserve integrity constraints on object behavior in application environments where objects of various classes dynamically interact with each other. In order to provide a stable design technique, a behavior model using the notion of the life cycle schema of a class is proposed. To model the aspect of behavioral abstraction of objects, the notion of schema refinement together with a diagrammatic representation technique is also defined. In this framework, a formalization of behavior constraints on objects which interact with each other is proposed together with its graphical representation. Verification rules of consistency of behavior constraints are also discussed. In order to perform certain functions, several partner objects of the same or different classes should collaborate establishing client-server relationships. The contract of a class is defined as a collection of responsibilities of a server class to a client class where each responsibility is specified in the form of the script. To achieve a high degree of systems integrity, a procedure to derive scripts from behavior constraints on collaborating partners is developed. It is also critical to evenly distribute responsibilities to partner objects. A delegation is placing a whole or a part of responsibilities of an object in charge of other objects. Based on the design principle delegation along the aggregation hierarchy,' a unified design approach to delegation that enables to reorganize scripts in constraints preserving way is proposed.

  • Cancellation Technique of Parasitics in Active Filter Design

    Takao TSUKUTAKI  Masaru ISHIDA  Yutaka FUKUI  

     
    LETTER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    957-960

    This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

  • Analysis of Excess Intensity Noise due to External Optical Feedback in DFB Semiconductor Lasers on the Basis of Mode Competition Theory

    Michihiko SUHARA  Minoru YAMADA  

     
    PAPER-Opto-Electronics

      Vol:
    E76-C No:6
      Page(s):
    1007-1017

    The generation mechanism for excess intensity noise due to optical feedback is analyzed theoretically and experimentally. Modal rate equations under the weakly coupled condition with external feedback are derived to include the mode competition phenomena in DFB and Fabry-Perot lasers. We found that the sensitivity of the external feedback strongly depends on design parameters of structure, such as the coupling constant of the corrugation, the facet reflection and the phase relation between the corrugation and the facet. A DFB laser whose oscillating wavelength is well adjusted to Bragg wavelength through insertion of a phase adjustment region becomes less sensitive to external optical feedback than a Fabry-Perot laser, but other types of DFB lasers revealing a stop band are more sensitive than the Fabry-Perot laser.

  • A Minimum-Latency Linear Array FFT Processor for Robotics

    Somchai KITTICHAIKOONKIT  Michitaka KAMEYAMA  

     
    PAPER-Speech Processing

      Vol:
    E76-D No:6
      Page(s):
    680-688

    In the applications of the fast Fourier transform (FFT) to real-world computation such as robot vision, high-speed processing with small latency is an important issue. In this paper, we propose a linear array processor for the minimum-latency FFT computation. The processor is constructed by identical butterfly elements (BE's). The key concept to minimize the latency is that each BE generates its output data immediately after its input data become available, with 100% utilization of its arithmetic unit. We also introduce the real-valued FFT to perform the complex-valued FFT. We utilize a double linear array structure so that the parallel processing can be realized without communication between the linear arrays. As a result, the hardware amount of a single BE is reduced to half that of conventional designs. The latency of the proposed FFT processor is greatly reduced in comparison with conventional linear array FFT processors.

  • A Method of Approximating Characteristics of Linear Phase Filters Utilizing Interpolation Technique in Combination with LMS Method

    Yoshiro SUHARA  Takashi MADACHI  Tosiro KOGA  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    911-916

    The approximation of the gain characteristics of linear phase FIR digital filters is reduced to the approximation by cosine polynomials. Therefore we can easily obtain an optimum solution under the LMS of Chebyshev error criterion. However the optimum solution does not always meet practical specifications, especially in the case where the gain is specified strictly at some angular frequencies. On the other hand in such a case, it is known that interpolation technique can be suitably applied for the approximation mentioned above. However, in this case, we encounter another difficulty in the approximation caused by interpolation. In order to overcome the above difficulty, this paper proposes a new method utilizing both of the interpolation and LMS techniques. Some parameters included in approximating functions are used to satisfy prescribed interpolating conditions and the other parameters are used to minimize the approximation error under the LMS criterion. In addition, interpolation technique is extended to include the case in which also higher derivatives are taken into interpolation conditions to make smooth interpolation. An example is shown to illustrate the effectiveness of the proposed method.

  • Proposal of a New Eye Contact Method for Teleconferences

    Kenji NAKAZAWA  Shinichi SHIWA  Tadahiko KOMATSU  Susumu ICHINOSE  

     
    PAPER

      Vol:
    E76-B No:6
      Page(s):
    618-625

    This paper discusses how to achieve eye contact in teleconferences attended by two or three conferees through a "Private Display Method." This method, which allows several images to be simultaneously displayed on a single screen, makes it possible to achieve eye contact. Each conferee can see a unique image, which is captured by a camera, which effectively acts as a substitute for the conferee in a counterparts room. The unique image is selected by a duoble-lenticular lens from images from two or three projectors. The effectiveness of the private display method has been demonstrated by ray-tracing simulation and by using a 50 double-lenticular screen. A prototype teleconferencing system for two persons was constructed with the 50 double-lenticular screen, a semi transparent silver coated mirror, two projectors and two cameras. Eye-contact with all counterparts can be achieved with the prototype teleconference system. The private display method is a promising way of achieving eye contact in teleconferences attended by two or three conferees.

  • A Hardware Architecture Design Methodology for Hidden Markov Model Based Recognition Systems Using Parallel Processing

    Jun-ichi TAKAHASHI  

     
    PAPER-Digital Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    990-1000

    This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.

  • Design and Analysis of OTA Switched Current Mirrors

    Takahiro INOUE  Oinyun PAN  Fumio UENO  Yoshito OHUCHI  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    940-946

    Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

  • Improvement of Performances of SC Sigma-Delta Modulators

    Kenichi SUGITANI  Fumio UENO  Takahiro INOUE  Takeru YAMASHITA  Satoshi NAGATA  

     
    PAPER-Methods and Circuits for Signal Processing

      Vol:
    E76-A No:6
      Page(s):
    931-939

    Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

  • Placement, Routing, and Compaction Algorithms for Analog Circuits

    Imbaby I. MAHMOUD  Toru AWASHIMA  Koji ASAKURA  Tatsuo OHTSUKI  

     
    PAPER-Algorithms for VLSI Design

      Vol:
    E76-A No:6
      Page(s):
    894-903

    The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

  • Some Hierarchy Results on Multihead Automata over a One-Letter Alphabet

    Yue WANG  Katsushi INOUE  Itsuo TAKANAMI  

     
    PAPER-Automaton, Language and Theory of Computing

      Vol:
    E76-D No:6
      Page(s):
    625-633

    The hierarchies of multihead finite automata over a one-letter alphabet are investigated. Let SeH(k) [NSeH(k) ] denote the class of languages over a one-letter alphabet accepted by deterministic [nondeterministic] sensing two-way k-head finite automata. Let H (k)s[NH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way deterministic [nondeterministic] k-head finite automata. Let SeH(k)s[NSeH(k)s] denote the class of sets of square tapes over a one-letter alphabet accepted by two-dimensional four-way sensing deterministic [nondeterministic] k-head finite automata. This paper shows that SeH(k) SeH(k1) and NSeH(k) NSeH(k1) hold for all k3. It is also shown that H(k)s[NH(k)s] H(k1)s[NH (k1)s] and SeH (k)s[NSeH(k)s] SeH(k1)s[NSeH(k1)s] hold for all k1.

  • Fuzzy Petri Net Representation and Reasoning Methods for Rule-Based Decision Making Systems

    Myung-Geun CHUN  Zeungnam BIEN  

     
    PAPER-Concurrent Systems, Discrete Event Systems and Petri Nets

      Vol:
    E76-A No:6
      Page(s):
    974-983

    In this paper, we propose a fuzzy Petri net model for a rule-based decision making system which contains uncertain conditions and vague rules. Using the transformation method introduced in the paper, one can obtain the fuzzy Petri net of the rule-based system. Since the fuzzy Petri net can be represented by some matrices, the algebraic form of a state equation of the fuzzy Petri net is systematically derived. Both forward and backward reasoning are performed by using the state equations. Since the proposed reasoning methods require only simple arithmetic operations under a parallel rule firing scheme, it is possible to perform real-time decision making with applications to control systems and diagnostic systems. The methodology presented is also applicable to classical (nonfuzzy) knowledge base systems if the nonfuzzy system is considered as a special case of a fuzzy system with truth values being equal to the extreme values only. Finally, an illustrative example of a rule-based decision making system is given for automobile engine diagnosis.

20961-20980hit(21534hit)