In this letter, we study on the sensitivity to the electrical stimulus pulse for biomedical electronics for the purpose to make a tactile vision substitution system for binds. We derive the equivalent circuit of finger by measuring sensitive voltages with various touch condition and various DC voltage. And we consider to the sensitivity of finger against electrical stimulus pulse. In order to convert the sense of sight to tactile sense, we consider four types of touch condition and various types of pulse. It is shown that the sensitivity of finger to electrical stimulus pulse is determined by duty-ratio, frequency, hight of pulse and the type of touch condition. In the case that duty-ratio is about 20%, frequency is within about 60-300Hz and touch condition is A-4 type, the sensitive voltage becomes the lowest. With this result, a tactile vision substitution system can be developed and the system will be used to transfer various infomations to blinds without paper.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

This paper describes a new method for the concurrent detection of faults in instruction level parallel (ILP) processors. This method uses the No OPeration (NOP) instruction slots that under branches, resource conflicts and some kind of data dependencies fill some of the pipelines (stages) in an ILP processor. NOPs are replaced by the copy of an effective instruction running in another pipeline. This allows the checking of the pipelines running the original instruction and its copy (ies), by the comparison of the outputs of their stages during the execution of the replicated instruction. We show some figures obtained for the application of this method to a two-pipeline superscalar processor.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

Three dimensional (3-D) optics offers potential advantages to the massively-parallel systems over electronics from the view point of information transfer. The purpose of this paper is to survey some aspects of the 3-D optical interconnection technology for the future massively-parallel computing systems. At first, the state-of-art of the current optoelectronic array devices to build the interconnection networks are described, with emphasis on those based on the semiconductor technology. Next, the principles, basic architectures, several examples of the 3-D optical interconnection systems in neural networks and multiprocessor systems are described. Finally, the issues that are needed to be solved for putting such technology into practical use are summarized.

This review presents research topics and results on digital signal processing in the last twenty years in Japan. The main parts of the review consist of design and analysis of multidimensional digital filters, multiple-valued logic circuits and number systems for signal processing, and general purpose signal processors.

In order to describe the flow passing through the glottis, we constructed a dynamic three-dimensional finite element model of the human larynx. The transient flow fields in the laryngeal model were calculated to examine the dynamic effects generated by the vocal fold vibration. A phase difference between the upper and lower edges of the vocal folds was included in the model to investigate the effect of the glottal shapes on pressure-flow relationships in the larynx during the vocal fold vibration. Using STAR-CD thermofluids analysis system, which is capable of treating the transient flow in moving-boundary situations with finite volume method, we solved the viscous incompressible Navier-Stokes equations to investigate the glottal flows and transglottal pressures as a function of the vocal fold vibration. The results were compared to the uniform glottis model and the theoretical model proposed by Ishizaka and Matsudaira, respectively. The effects of dynamic factors on the pressure distributions and flow patterns in the larynx resulting from the vocal-fold vibration were also discussed.

Sea clutter was measured using an X-band radar at very high grazing angles between 8.2 and 17.5. The sea state was 7 with the wave height of 6 to 9m. The wind velocity was 25m/s. It is shown that sea clutter amplitudes obey the log-normal and K distributions using the Akaike Information Criterion (AIC) , which is more rigorous fit to the distribution to the data than the least squares method.

We observed a ship as a radar target embedded in sea clutter using a millimeter wave radar. The shape of the ship and sea clutter were discriminated by using texture analysis in image processing. As a discriminator, a nonlinear transformation of a local pattern was defined to deal with high order statistics.

Embossed disks with discrete magnetic tracks and servo marks are proposed and evaluated. The tracks and the servo marks are made by etching the glass substrate. The guard band depth was decided to be 0.2 µm. Using the disks, the head positioning accuracy of 0.09µm (rms) and the recording density of 192 tracks per millimeter were demonstrated.

This paper describes the architecture and simulated performance of a proposed Integrated Memory Array Processor (IMAP). The IMAP is an LSI which integrates a large capacity memory and a one dimensional SIMD processor array on a single chip. The IMAP holds, in its on-chip memory, data which at the same time can be processed using a one dimensional SIMD processor integrated on the same chip. All processors can access their individual parts of memory columns at the same time. Thus, it has very high processor-memory data transfer bandwidth, and has no memory access bottleneck. Data stored in the memory can be accessed from outside of the IMAP via a conventional memory interface same as a VRAM. Since the SIMD processors on the IMAP are configured in a one dimensional array, multiple IMAPs could easily be connected in series to create a larger processor and memory configuration. To estimate the performance of such an IMAP, a system architecture and instruction set were first defined, and on the basis of those two, a simulator and an assembly language were then developed. In this paper, simulation results are presented which indicate the performance of an IMAP in both image processing and artificial neural network calculations.

A radial line slot antenna (RLSA) is a high gain and high efficiency planar array. A single-layered RLSA is much simple in structure but the slot length must be varied to synthesize uniform aperture illumination. These are now commercialized for 12GHz band DBS reception. In RLSAs, considerable power is dissipated in the termination as is common to other traveling wave antennas; the uniform aperture illumination is not the optimum condition for high gain in RLSAs. Authors proposed a theoretical method reducing the termination loss for further efficiency enhancement. This paper presents the measured performances of the SL-RLSAs of this design with non-uniform aperture illumination. The efficiency enhancement of about 10% is observed; the measured gain of 36.7dBi (87%) and 32.9dBi (81%) for a 0.6mφ and 0.4mφ antennas respectively verify this technique.

Current status and critical issues of the material and device technology towards constructing new architecture LSIs based on quantum-mechanical principles are reviewed in an attempt to draw attention of systems workers to the field. Limitations of the present-day LSI architecture are discussed from the viewpoints of material science and device physics. New quantum mechanical phenomena in the quantum structures are reviewed. Then, key material and processing issues for fabrication of desired quantum structures are briefly discussed. Finally, the basic operation principles the quantum devices and possible architectures of quantum LSIs are discussed.

Intermittent chaos was observed in the silicon thyristor circuit without external elements of L and C, under the condition of ac excitation at the anode. Lorenz plot reconstructed from the experimental waveform and the numerical simulation of this kind of intermittency fairly agreed with each other.

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

The recent non von Neumann chip architectures are mainly classified into the AI architecture and the neural architecture. We focus on these two categories, and introduce the representatives each with a brief history. The AI chip architecture is difficult to escape essentially from the von Neumann architecture as far as it is language-oriented. The neural architecture, however, may yield an essentially new computer architecture, when the new device technologies will support it. In particular, the optoelectronics and the quantum electronics will provide a lot of powerful technologies.

To investigate necessary conditions for the object recognition by simulations using neural network models is one of ways to acquire suggestions for understanding the neuronal representation of objects in the brain. In the present study, we trained a three layered neural network to form a geometrical feature representation in its output layer using back-propagation algorithm. After training using 73 learning examples, 65 testing patterns made by various combinations of above features could be recognized with the network at a rate of 95.3% appropriate response. We could classify four types of hidden layer units on the basis of effects on the output layer.

Recently, there has been increasing interest in Code Division Multiplex (CDM) systems. We reported the CDM system using the -chip shift multiplex operation. So far the performance of this system evaluated under the optimum . In this letter, we evaluate an influence of the phase difference between the groups on BER performance in 2M-plex system.

An estimation method of region is presented, in which a solution path of the so-called Newton type homotopy equation in guaranteed to exist, it is applied to a certain class of uniquely solvable nonlinear equations. The region can be estimated a posteriori, and its upper bound also can be estimated a priori.

To improve measurement accuracy and speed, a switched-capacitor capacitance measurement circuit with the vernier scale is developed. Its process consists of a coarse measurement by charge-balancing A-D conversion and a fine measurement by single-slope A-D conversion. a prototype using discrete components confirms the principles of operation.