Algorithms for computing channel capacity have been proposed by many researchers. Recently, one of the authors proposed an efficient algorithm using Newton's method. Since this algorithm has local quadratic convergence, it is advantageous when we want to obtain a numerical solution with high accuracy. In this letter, it is shown that this algorithm can be extended to the algorithm for computing the constrained capacity, i.e., the capacity of discrete memoryless channels with linear constraints. The global convergence of the extended algorithm is proved, and its effectiveness is verified by numerical examples.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

This paper presents a hardware architecture design methodology for hidden markov model based recognition systems. With the aim of realizing more advanced and user-friendly systems, an effective architecture has been studied not only for decoding, but also learning to make it possible for the system to adapt itself to the user. Considering real-time decoding and the efficient learning procedures, a bi-directional ring array processor is proposed, that can handle various kinds of data and perform a large number of computations efficiently using parallel processing. With the array architecture, HMM sub-algorithms, the forward-backward and Baum-Welch algorithms for learning and the Viterbi algorithm for decoding, can be performed in a highly parallel manner. The indispensable HMM implementation techniques of scaling, smoothing, and estimation for multiple observations can be also carried out in the array without disturbing the regularity of parallel processing. Based on the array processor, we propose the configuration of a system that can realize all HMM processes including vector quantization. This paper also describes that a high PE utilization efficiency of about 70% to 90% can be achieved for a practical left-to-right type HMMs.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Behavior modeling of objects is critical in object-oriented design. In particular, it is essential to preserve integrity constraints on object behavior in application environments where objects of various classes dynamically interact with each other. In order to provide a stable design technique, a behavior model using the notion of the life cycle schema of a class is proposed. To model the aspect of behavioral abstraction of objects, the notion of schema refinement together with a diagrammatic representation technique is also defined. In this framework, a formalization of behavior constraints on objects which interact with each other is proposed together with its graphical representation. Verification rules of consistency of behavior constraints are also discussed. In order to perform certain functions, several partner objects of the same or different classes should collaborate establishing client-server relationships. The contract of a class is defined as a collection of responsibilities of a server class to a client class where each responsibility is specified in the form of the script. To achieve a high degree of systems integrity, a procedure to derive scripts from behavior constraints on collaborating partners is developed. It is also critical to evenly distribute responsibilities to partner objects. A delegation is placing a whole or a part of responsibilities of an object in charge of other objects. Based on the design principle delegation along the aggregation hierarchy,' a unified design approach to delegation that enables to reorganize scripts in constraints preserving way is proposed.

This paper describes a 0.8-µm CMOS LSI developed for a 156-Mb/s serial interface in ATM switching systems. Recently, there have been increasing problems of connector pin neck and higher power consumption when enhancing switching system capacity. To overcome these problems, we have developed an LSI with a high-speed interface by using CMOS technology to achieve low power consumption. A low-swing differential signal level is used to achieve 156-Mb/s data transmission. We named this new circuit technique ALTS (Advanced Low-level Transmission circuit System). Using the LSI, transmission can be achieved between boards or racks through a 10-meter twisted pair cable. The LSI has a 156-Mb/s transmitter-receiver, a serial-to-parallel converter and a parallel-to-serial converter. It performs 19.5-Mb/s parallel data/156-Mb/s serial data conversion and 156-Mb/s serial data transmission. In addition, it has a bit phase synchronizer and cell synchronizer, which enables it to transmit and synchronize serial data without a paralleled clock or a paralleled cell top signal, by distributing a common 156-MHz clock and a common cell top signal to the whole system. We evaluated the bit error rate and timing margin on data transmission under several conditions. The results show that we can apply this LSI to commercially available ATM switching systems. This paper also describes methods of expanding switch capacity and transmitting 624-Mb/s data using this LSI.

We describe an approach for modelling a person's face for model-based coding. The goal is to estimate the 3D shape by combining the contour analysis and shading analysis of the human face image in order to increase the quality of the estimated 3D shape. The motivation for combining contour and shading cues comes from the observation that the shading cue leads to severe errors near the occluding boundary, while the occluding contour cue provides incomplete surface information in regions away from contours. Towards this, we use the deformable model as the common level of integration such that a higher-quality measurement will dominate the depth estimate. The feasibility of our approach is demonstrated using a real facial image.

A least squares approximation method of recursive digital filters for finite interval response with zero value outside the interval is presented. According to the characteristic of the method, the modified Gauss Method is utilized in iteratively determining design parameters. Convergence, together with the stability of the resulting filter, are guaranteed.

This paper presents a new Hypermedia communication platform supported by the new digital image medium of super high definition (SHD) images. This new image communication platform will encourage the integration of all existing media to realize rich and realistic visual communication over B-ISDN. SHD images have a resolution of more than 20482048 pixels and the frame rate is more than 60 frames/sec. To achieve an real-time compression of SHD moving images, parallel signal processing systems with peak performance of 0.5 Tera Flops will be necessary. The specification requirements, signal processing and communication technologies needed to achieve SHD image communication are discussed. The relationship of hypermedia to SHD images is also examined.

A superresolution technique is considered for use in antenna gain measurements. A modification of the MUSIC algorithm is employed to resolve incident signals separately in the time domain. The modification involves preprocessing the received data using a spatial scheme prior to applying the MUSIC algorithm. Interference rejection in the antenna measurements using the fast Fourier transform (FFT) based techniques have been realized by a recently developed vector network analyzer, and its availability has been reported in the literature. However, response resolution in the time domain of these conventional techniques is limited by the antenna bandwidth. The MUSIC algorithm has the advantage of being able to eliminate unwanted responses when performing antenna measurements in situations where the antenna band-width is too narrow to support FFT based techniques. In this paper, experimental results of antenna gain measurements in a multipath environment show the accuracy and resolving power of this technique.

Behavior of solutions related to an accuracy exp(-1/ε) is studied. Computer results are given, and examined from the view-point of non-standard analysis. The experimental results raise some important questions on the computer study of slow-fast systems.

When a new fabrication process is set up, especially in layout design for functional cells, of practical importance is how to make the best use of layout resources so far accumulated in old fabrication processes. Usually layout data of each element are expressed mostly in terms of positional coordinate values, and hence it is extremely tedious to modify them at every change of design rules for a new fabrication technology. To cope with this difficulty, the present paper describes an automatic recycling scheme for layout resources accumulated dedicatedly for functional cell generation. The main subject of this scheme is to transform given layout data into a layout description format expressed in layout parameters. Once layout data are parameterized, layout patterns of functional cells can be reconstructed simply by tuning up parameters in accordance with a new set of design rules. A part of implementation results are also shown.

This paper describes bandpass filters using linear tapered transmission line resonators (LTLR's). Bandpass filters are designed on the basis of the approximate description of LTLR's with cascaded multi-sections of uniform transmission lines whose widths are slightly different. By this design method, the fundamental characteristics of LTLR's and filter design parameters can be easily obtained using a general-purpose microwave circuit simulator. Trial LTLR bandpass filters showed excellent performance such as low insertion losses and the ability to control spurious responses, then their measured responses indicated close correspondence with the design results.

In the applications of the fast Fourier transform (FFT) to real-world computation such as robot vision, high-speed processing with small latency is an important issue. In this paper, we propose a linear array processor for the minimum-latency FFT computation. The processor is constructed by identical butterfly elements (BE's). The key concept to minimize the latency is that each BE generates its output data immediately after its input data become available, with 100% utilization of its arithmetic unit. We also introduce the real-valued FFT to perform the complex-valued FFT. We utilize a double linear array structure so that the parallel processing can be realized without communication between the linear arrays. As a result, the hardware amount of a single BE is reduced to half that of conventional designs. The latency of the proposed FFT processor is greatly reduced in comparison with conventional linear array FFT processors.

This letter presents a technique to cancel the parasitic effects of operational amplifier (op amp) in active filter design. To minimize the effects, an op amp model considering the parasitics (i.e. both parasitic poles and zeros) is utilized. It is shown that undesirable factors in the transfer function due to the parasitics can be canceled well by predistorting the passive element values of the circuit. As an example, an active-R highpass filter is evaluated both theoretically and numerically. In this way, the proposed technique can be effectively incorporated into the design of active filters.

An active feedback resonator (AFR) is a kind of circuit which functions as a high unloaded Q resonator. The AFR employs an active feedback loop which compensates for the energy loss of a conventional microwave resonator. Owing to an active element in the AFR, thermal noise should be taken into account when designing the AFR. In order to simplify a circuit design using the AFR we introduced noise temperature (Tn) for the AFR. In addition, we describe the AFR design which gives minimum noise temperature. Finally, the noise temperature, measured in an AFR as a band elimination filter, is compared with the theoretical value to evaluate the AFR.

The approximation of the gain characteristics of linear phase FIR digital filters is reduced to the approximation by cosine polynomials. Therefore we can easily obtain an optimum solution under the LMS of Chebyshev error criterion. However the optimum solution does not always meet practical specifications, especially in the case where the gain is specified strictly at some angular frequencies. On the other hand in such a case, it is known that interpolation technique can be suitably applied for the approximation mentioned above. However, in this case, we encounter another difficulty in the approximation caused by interpolation. In order to overcome the above difficulty, this paper proposes a new method utilizing both of the interpolation and LMS techniques. Some parameters included in approximating functions are used to satisfy prescribed interpolating conditions and the other parameters are used to minimize the approximation error under the LMS criterion. In addition, interpolation technique is extended to include the case in which also higher derivatives are taken into interpolation conditions to make smooth interpolation. An example is shown to illustrate the effectiveness of the proposed method.

In this paper, the characteristics of microstrip lines near the edge of dielectric substrate are analyzed by improving the rectangular boundary division method. The numerical results indicate the changes of the characteristics of a microstrip line when the strip conductor is closely located to the edge. When the distance the dielectric substrate edge to the strip conductor is less than the thickness of dielectric substrate, the effects of the edge on the line characteristics are no longer negligible. The numerical results in this paper show high computation accuracy without increasing computation time. Our improvement is effective for the analysis of the microstrip lines both for the narrow strip conductor and the strip conductor close to the edge. The relative errors between the numerical results and the measured values are less than 1.2%.

This paper discusses how to achieve eye contact in teleconferences attended by two or three conferees through a "Private Display Method." This method, which allows several images to be simultaneously displayed on a single screen, makes it possible to achieve eye contact. Each conferee can see a unique image, which is captured by a camera, which effectively acts as a substitute for the conferee in a counterparts room. The unique image is selected by a duoble-lenticular lens from images from two or three projectors. The effectiveness of the private display method has been demonstrated by ray-tracing simulation and by using a 50 double-lenticular screen. A prototype teleconferencing system for two persons was constructed with the 50 double-lenticular screen, a semi transparent silver coated mirror, two projectors and two cameras. Eye-contact with all counterparts can be achieved with the prototype teleconference system. The private display method is a promising way of achieving eye contact in teleconferences attended by two or three conferees.