This paper investigates the behavior of one-dimensional discrete-time binary cellular neural networks with both the A- and B-templates and gives the necessary and sufficient conditions for the above network to be stable for unspecified fixed boundaries.

In this paper, we present the following schemes for a content-based image search: (1) A fast image search algorithm that can significantly reduce similarity calculation compared to a full comparison of every database image. (2) A compact image representation scheme that can describe the global/local information of the images and provide successful retrieval performance. For fast searches, a tree is constructed by successfully dividing nodes into the desired depth level by working from the root to the leaf nodes using the k-means algorithm. When the query is completed, we traverse the tree top-down by minimizing the route taken between the query image and node centroid until we meet the undivided nodes. Within undivided nodes, the algorithm of triangle inequality is used to find the images most similar to the query. For compact image representation, RGB color histogram features which are quantized into 16 bins each of the R, G, and B channels are used for global information. Dominant hue, saturation, and value which are extracted from the HSV joint histogram in the localized regions within the image are used for local information. These features are sufficiently compact to index image features in large database systems. For experiments on the retrieval efficiency, the use of the proposed method provided substantial performance benefits by reducing the image similarity calculation up to an average of a 96% and for experiments on the retrieval effectiveness, in the best case, it provide a 36.8% recall rate for a whale query image and a 100% precision rate for an eagle query image. The overall performance was a 20.0% recall rate and a 72.5% precision rate.

Let us introduce n ( 2) mappings fi (i=1,2,,n) defined on complete linear metric spaces (Xi-1, ρ) (i=1,2,,n), respectively, and let fi:Xi-1 Xi be completely continuous on bounded convex closed subsets Xi-1(0) Xi-1, (i=1,2,,n 0), such that fi(Xi-1(0)) Xi(0). Moreover, let us introduce n set-valued mappings Fi : Xi-1 Xi (Xi)(the family of all non-empty closed compact subsets of Xi), (i=1,2,,n 0). Here, we have a fixed point theorem on the successively recurrent system of set-valued mapping equations: xi Fi(xi-1, fi(xi-1)), (i=1,2,,n 0). This theorem can be applied immediately to analysis of the availability of system of circular networks of channels undergone by uncertain fluctuations and to evaluation of the tolerability of behaviors of those systems. In this paper, mathematical situation and detailed proof are discussed, about this theorem.

Cellular Neural Networks (CNNs) have been developed as a high-speed parallel signal-processing platform. In this paper, a generalized two-layer cellular neural network model is proposed for image processing, in which two templates are introduced between the two layers. We found from the simulations that the two-layer CNNs efficiently behave compared to the single-layer CNNs for the many applications of image processing. For examples, simulation problems such as linearly non-separable task--logic XOR, center point detection and object separation, etc. can be efficiently solved with the two-layer CNNs. The stability problems of the two-layer CNNs with symmetric and/or special coupling templates are also discussed based on the Lyapunov function technique. Its equilibrium points are found from the trajectories in a phase plane, whose results agree with those from simulations.

This letter proposes a packet length-based group-wise transmission (LGT) rate scheduling scheme for non-real time data service for the uplink of direct sequence code division multiple access (DS/CDMA) system using the burst switching scheme to support the integrated voice/data service. The LGT scheme optimally determines two different rate groups and their optimal data rates so as to minimize the average packet transmission delay. It has shown that the packet transmission delay performance can be significantly improved over the conventional single-rate packet transmission scheme for integrated voice/data service. Furthermore, a main feature of the proposed scheme is simplicity in its implementation.

In this paper, we present new stability conditions for a class of large-scale hybrid dynamical systems composed of a number of interconnected hybrid subsystems. The stability conditions are given in terms of discontinuous Lyapunov functions of the stable hybrid subsystems. Furthermore, the stability conditions are represented by LMIs (Linear Matrix Inequalities) which are computationally tractable.

This paper presents a method of simple adaptive control (SAC) for nonlinear systems using Elman recurrent neural networks (ERNNs). The control input is given by the sum of the output of a simple adaptive controller and the output of the ERNN. The ERNN is used to compensate the nonlinearity of plant dynamics that is not taken into consideration in the usual SAC. The role of the ERNN is to construct a linearized model by minimizing the output error caused by nonlinearities in the control systems.

Hypercomplex coefficient digital filters provide several attractive advantages such as compact realization with reduced system order, inherent parallelism. However, they also possess a drawback in that a multiplier requires a large amount of computations. This paper proposes a computationally efficient implementation of digital filters whose coefficient is a type of hypercomplex number; a bicomplex number. By decomposing a bicomplex multiplier into two parallel complex multipliers, we show that hypercomplex digital filters can be implemented as two parallel complex digital filters. The proposed implementation offers more than a 60% reduction in the count of real multipliers.

In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm 800 µm and it dissipates about 210 mW at 3 V power supply. The INL is within 1 LSB and DNL is within 1 LSB, respectively. The SNR is about 43 dB, when the input frequency is 10 MHz at 200 MHz clock frequency.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

In this paper, a new adaptive method is suggested using the complementally transformed minimum variance technique for the purpose of suppressing interference in additive white and colored Gaussian noise channels. The method is based on interference suppression by way of the resulting projection weight. The multiple access causes an interference problem in the code-division multiple access systems. An efficient adaptive algorithm should be used to suppress this interference for the improvement of system performance. Analytical and simulation results show that the new adaptive method has fast convergence rate and offers significant performance gain over the conventional detector, the MMSE detector, and the linear decorrelator. Finally, multipath fading induced performance loss, which leads to error probability floor, is established for the proposed method with combining schemes and shown by computer simulation.

Adaptive optimization of the notch bandwidth of a lattice-based adaptive infinite impulse response (IIR) notch filter is presented in this paper. The filter is used to improve the performance of a direct sequence spread spectrum (DSSS) binary phase shift keying (BPSK) communication system by suppressing a narrow-band interference at the receiver. A least mean square (LMS) algorithm used to adapt the notch bandwidth coefficient to its optimum value which corresponds to the maximum signal to noise ratio (SNR) improvement factor is derived. Bit error rate (BER) improvement gained by the DSSS communication system using the filter with the optimized notch bandwidth is also shown. Computer simulation results are compared with those obtained analytically to demonstrate the validity of theoretical predictions for various received signal parameters.

It is widely known that the family of projection filters includes the generalized inverse filter, and that the family of parametric projection filters includes parametric generalized projection filters. However, relations between the family of parametric projection filters and constrained least squares filters are not sufficiently clarified. In this paper, we consider relations between parameter estimation and image restoration by these families. As a result, we show that the restored image by the family of parametric projection filters is a maximum penalized likelihood estimator, and that it agrees with the restored image by constrained least squares filter under some suitable conditions.

A hierarchical timing adjuster that operates with intermittent adjustment has been developed for use in low-power DDR SDRAMs. Intermittent adjustment reduces power consumption in both coarse- and fine-delay circuits. Furthermore, the current-controlled fine-tuning of delay is free of short-circuit current and achieves a resolution of about 0.1 ns. In a design with 0.16-µm node technology, these techniques make the hierarchical timing adjuster able to reduce the operating current to 4.8 mA, which is 20% for the value in a conventional scheme with every-cycle measurement. The proposed timing adjuster achieves a three-cycle lock-in and only generates an internal clock pulse that has coarse resolution in the second cycle. The circuit operates over the range from 60 to 150 MHz, and occupies 0.29 mm2.

This paper introduces an improved multistage parallel interference cancellation (PIC) technique that uses the reverse-link synchronous transmission technique (RLSTT) to improve the estimation of data at the initial stage. Because the subtraction of an interfering signal based on an incorrect bit decision quadruples the interference power for that signal, the relatively high decision bit error rate (BER) may lead to a poor cancellation or even a higher BER at the following stages. The RLSTT is a robust approach which takes into account the fact the tentative decision at the earlier stages is less reliable than the following stages and makes the earlier cancellation more reliable. The analysis demonstrates that a better transmission performance can be achieved by using the RLSTT at the initial stage of PIC.

A new algorithm for synthesizing binary threshold neural networks (BTNNs) is proposed. A binary (Boolean) input-output mapping that can be represented by minimal sum-of-product (MSP) terms is initially obtained from training data. The BTNN is then synthesized based on an MSP term grouping method. As a result, a fast and optimal realization of a BTNN can be obtained. Examples of both feedforward and recurrent BTNN synthesis used in a parallel processing architecture are given and compared with other existing methods.

A circuit that carries out an Hadamard transform of an input image using the pulse width modulation technique is proposed. The proposed circuit architecture realizes the function of an Hadamard transform with a full-size pixel image. A test chip that we designed and fabricated integrates 64 64 pixels in a 4.9 mm 4.9 mm area, with 0.35 µm CMOS technology. The functional operation and linearity of this chip are measured. An image processing application utilizing this chip is demonstrated.

This paper presents a novel low-energy memory design technique based on variable analysis for on-chip data memory (RAM) in application-specific systems, which called VAbM technique. It targets the exploitation of both data locality and effective data width of variables to reduce energy consumed by data transfer and storage. Variables with higher access frequency and smaller effective data width are assigned into a smaller low-energy memory with fewer bit lines and word lines, placed closer the processor. Under constraints of the number of memory banks, VAbM technique use variable analysis results to perform allocating and assigning on-chip RAM into multiple banks, which have different size with different number of word lines and different number of bit lines tailored to each application requirements. Experimental results with several real embedded applications demonstrate significant energy reduction up to 64.8% over monolithic memory, and 27.7% compared to memory designed by memory banking technique.

We describe a method of compensating temperature fluctuation by a linear-time-warping processing in a sound reproduction system. This technique is applied to impulse responses of room transfer functions, to achieve a high-quality sound reproduction system, particularly one that treats high-frequency components. First, the impulse responses are measured before and after temperature fluctuation, and the former are converted to the latter by the proposed process. Next, we design inverse filters for the system, and evaluate the improvement of the reproduction accuracy and spectrum distortion. By the compensation method, we can improve the reproduction accuracy at any frequency. Moreover, we propose an adaptive algorithm for the estimation of a suitable warping ratio, using the observed signal of reproduced sound obtained at only one control point. Using the proposed algorithm, we can improve the reproduction accuracy at each control point by about 14 dB, in which a difference in temperature is 1.4.

A low-power-consumption 6-bit pipelined analog-to-digital converter for use in a BluetoothTM RF transceiver has been developed. The RF transceiver chip was fabricated using a 0.35-µm BiCMOS process, and the A/D converter is based on CMOS technology for digital logic. To reduce the power consumption of the converter, we used a look-ahead pipeline architecture to reduce the required settling time of an amplifier in the critical path of the converter. We show that through this reduction, amplifier power consumption of 600 µA can be reduced to 250 µA to achieve a 13-MHz conversion rate. We have also developed a low-power two-capacitor switched-capacitor common-mode feedback circuit which enables an offset cancellation of an amplifier during the reset phase. Offset cancellation is used in each stage of the S/H amplifier to reduce the overall offset of the converter. It achieves an effective number of bits of 5.7 at a conversion rate of 13 Msps and 5.0 at 26 Msps. The residual offset of the converter is only 4 mV. It has a low total current consumption of 3.2 mA at 13 Msps and a supply voltage of 2.8 V.