The ranging algorithm allows active stations to measure their distances to the headend for synchronization purpose in Hybrid Fiber Coax (HFC) networks. A practicable mechanism to resolve contention among numerous stations is to randomly delay the transmission of their control messages. Since shorter contention cycle time increases slot throughput, this study develops three mechanisms, fixed random delay, variable random delay, and optimal random delay, to minimize the contention cycle time. Simulation demonstrates that the optimal random delay effectively minimizes the contention cycle time and approaches the theoretical optimum throughput of 0.18 from pure ALOHA. Furthermore, over-estimation reduces the impact on contention cycle time more than under-estimation through sensitivity analysis, and both phenomenon damage slot throughput. Two estimation schemes, maximum likelihood and average likelihood, are thereby presented to estimate the number of active stations for each contention resolution round. Simulation proofs that the proposed estimation schemes are effective even when the estimated number of active stations in initial contention round is inaccurate.

In this paper, the performance of multi-stage parallel interference cancellation receiver using forward-backward filtering channel estimation is evaluated for the W-CDMA uplink. The channel estimation employs a non-causal forward-backward-multiplication-method filter, which was originally proposed for the reception of W-CDMA random access. Results of link level simulations for data and voice traffic scenarios over Pedestrian A and Vehicular A channels are discussed in comparison with the conventional channel estimation methods of 1-slot pilot averaging, 1-slot averaging, and weighted multiple slot averaging. It is shown that the forward-backward filtering channel estimation improves performances of the interference cancellation receiver as well as that of the ordinary Rake receiver in both Pedestrian A and Vehicular A channels. With its features of short processing delay and low complexity, the forward-backward filtering channel estimation is suitable for practical implementations of multi-stage interference cancellation receivers.

A practical EB-testing-pad method, that enables higher observability of multilevel wiring LSIs without any increase of chip size, has been evaluated by using actual 0.25-µm SIMOX/CMOS devices. First, an 80k-gate logic LSI with testing pads was developed, and it was proved that observability improves from 17% to 87%. Next, two kinds of gate-chain TEGs (test element groups), with and without testing pads was developed to investigate the influence of testing pads on gate delay. It was found that the circuit delay increase due to the pads is very small, less than 2.7%. It was also found that capacitances from neighboring wires will increase only by at most 3% due to the testing pads. Thus, the testing pad method has been proved to be extremely effective in improving observability without any overhead in design.

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.

Write linear density limit is defined to analyze the magnetic recording process in computer hard disk drives at extremely high recording densities. The digital data with pseudo random sequences are recorded numerically in longitudinal media at different densities by a micromagnetic simulation model. A thin film write head and an ideal GMR read head are utilized in the record and read-back process, respectively. A novel method has been utilized to study the write linear density limit: the simulated read back voltage and the respected linear superposed pulses are compared to find the distortion in the record process. When a severe distortion shows up, the corresponding linear density is considered as the write linear density limit. By the novel method, the write linear density limit is analyzed with different parameters of the recording media.

A debug system for heterogeneous multiple processors in a single chip has been developed. The system consists of the debug interface circuit integrated on the chip, the interface circuit board between the chip and PC, and the debug software implemented on a PC. This debug system has been designed for a multimedia communication processor, which includes an original video processor core, a RISC processor, and a DSP. The RISC processor controls the Video Processing Unit that includes an original video processor and other hardware functions. While in debug mode, the external debugger can control the Video Processing Unit in the same manner as the RISC processor. The JTAG based interface circuit contains registers for bus transaction for command, address, and data to be written, etc. and a bus transaction sequencer. In fact, this system can realize the same bus transaction control as the RISC processor's. By applying proposed debug system, simultaneous debug of the RISC Processing Unit and the Video Processing Unit can be realized. This allows problems to be investigated more quickly and the total time required for debugging is efficiently reduced. Without this technology an estimated 19 weeks is required to debug the chip, whereas use of this technology allowed debugging to be completed in 9 weeks.

An adaptive array antenna should be applied for suppression of CCI in the spatial domain. However, the adaptive array antenna has some problems as follows. Because the adaptive array antenna takes a long time to converge to the optimum antenna weights, it's hard to track in case of quick varying channel. On the other hand, processing burden increases with the number of elements in the array antenna. To solve these problems, we propose an adaptive array antenna using array antenna as element antennas, the so-called "Layered array antenna." At the 1st layer, sector area are defined. We can change the sector areas according to the DOA distribution, because the sector areas are defined by the antenna weights. At the 2nd layer, MMSE is performed. Interference that couldn't be suppressed at the 1st layer is suppressed at the 2nd layer. By the proposed system, we confirmed higher convergence speed while relieving processing complexity.

Test compression/decompression is an efficient method for reducing the test application cost. In this paper we propose a test generation method for obtaining test-patterns suitable to test compression by statistical coding. In general, an ATPG generates a test-pattern that includes don't-care values. In our method, such don't-care values are specified based on an estimation of the final probability of 0/1 occurrence in the resultant test set. Experimental results show that our method can generate test patterns that are able to be highly compressed by statistical coding, in small computational time.

This paper proposes a test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits with DFT where hierarchical test generations are applicable. Moreover, a heuristic algorithm for a compacted test plan table generation is proposed. The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.

This paper presents a practical fault model for delay testing, called a multiple-threshold gate-delay fault model, to obtain high quality tests that guarantee the detection of delay faults for various extra-delays. Fault efficiencies for multiple thresholds of the extra-delay are introduced as a coverage metric that describes the quality of tests. Our approach guarantees that each gate-delay fault is tested on the path that is almost the longest one passing through the faulty line by using two-pattern tests with pattern-independent timing. We present the procedures of the path selection, fault simulation, and the test generation, where the path-status graph technique is used as not to rely on the enumeration of paths. Experimental results for benchmark circuits demonstrate that the proposed metric gives useful information that transition fault efficiency cannot, and that the proposed test generation can achieve high fault efficiencies for multiple-threshold gate-delay faults.

The effect of a nonmagnetic hcp-underlayer on the epitaxial growth of CoCr19Pt10 magnetic layers on substrates of Al2O3(0001) single-crystal has been investigated. Thin films of (0001)-oriented single-crystal CoCr19Pt10 were obtained by employing non-magnetic underlayers of CoCr25Ru25 and CoCr25Ru25/Ti, while thin films of polycrystalline CoCr19Pt10 were grown after the deposition of underlayers of TiCr10 and CoCr40. The growth of thin film CoCr19Pt10 on a Ti(0001) underlayer was interpreted as quasi-hetero-epitaxial where the continuity of the lattice across the interface is disturbed while the overall crystallographic relationship between the two layers is maintained. A thin film of epitaxially grown CoCr19Pt10 has a compositional variation of a few percent across the film plane in terms of elements that forms the alloy.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

This paper deals with formal verification of high-level designs, in particular, symbolic comparison of register-transfer-level descriptions and behavioral descriptions. We use state machines extended by quantifier-free first-order logic with equality, as models of those descriptions. We cannot adopt the classical notion of equivalence for state machines, because the signals in the corresponding outputs of such two descriptions do not change in the same way. This paper defines a new notion of consistency based on signal-transitions of the corresponding outputs, and proposes an algorithm for checking consistency of those descriptions, up to a limited number of steps from initial states. As an example of high-level designs, we take a simple hardware/software codesign. A C program for digital signal processing called PARCOR filter was compared with its corresponding design given as a register-transfer-level description, which is composed of a VLIW architecture and assembly code. Since this example terminates within approximately 4500 steps, symbolic exploration of a finite number of steps is sufficient to verify the descriptions. Our prototype verifier succeeded in the verification of this example in 31 minutes.

A performance comparison is developed between a chaotic communication system and a spread spectrum system with similar features in terms of bandwidth and transceiver structure but based on more conventional Gold sequences. Comparison is made in the presence of noise and multipath contributions which degrade the channel quality. It is shown that, because of its more favourable correlation properties, the chaotic scheme exhibits lower error rates, at a parity of the bandwidth expansion factor. The same favourable correlation properties are also used to explain and show, through a numerical example, the benefits of chaotic segments in a multi-user environment.

We propose bit error rate (BER) evaluation methods for a trellis coded modulation (TCM) scheme over a Rayleigh fading channel by using importance sampling (IS). The simulation probability density function for AWGN and Rayleigh fading is separately designed. For efficient simulation of a system model with finite interleaver, frequency of the generation of fading sequences is reduced. The proposed method gives a good BER estimates over a Rayleigh fading channel.

Low-profile inverter power supplies are increasingly required for backlight systems of liquid crystal displays (LCDs). A great deal of attention has been focused on the application of piezoelectric transformers (PTs) to such power supplies. To miniaturize PT inverters still further, PTs need to have sufficient high voltage-step-up-ratio, which can be achieved by a multilayered PT. First, this paper describes a method for simulating such performance using a distributed constant equivalent circuit model. The results of the simulation for a multilayered PT operated in the third order longitudinal vibration mode show that the resistance of internal electrodes causes the dominant loss factor. Next, a power inverter incorporating the multilayered PT was fabricated. This power inverter can be operated over a wide input DC voltage range from 7-20 V. Regarding a conventional inverter drive circuit, when input DC voltage range was extended, the inverter efficiency remarkably decreased. For the reason, we developed a new inverter circuit, which is equipped with an automatic drive voltage control circuit to maintain the drive voltage to the PT at a constant value. As a result, the fabricated power inverter exhibited more than 90% overall efficiency and 3.5 W output power, which is enough to light up a 12.1-inch color LCD. The maximum luminance efficiency on a light transmission plate of the backlight was as high as 30 cd/m2/W.

This paper proposes a channel monitor-based unequal error protection scheme using a dynamic OFDM subcarrier assignment technique for broadband video transmission systems in frequency selective fading environments. In the proposed system, to achieve stable regeneration of the received video, subcarriers with relatively high channel gain are assigned to the high priority data (HPD) in the MPEG data. To further guarantee a required transmission quality of the HPD, the proposed system also employs subcarrier transmission power control with delay profile information (DPI) feedback-type channel estimation technique. Computer simulation confirms that the proposed technique is effective in preventing quality degradation with about 20 dB lower transmission power than the conventional systems in frequency selective fading environments.

This paper presents an optimum antenna diversity combining method associated with despreading that employs Minimum Mean Square Error (MMSE) combining over the frequency domain in a frequency-selective fading channel for forward link Orthogonal Frequency and Code Division Multiplexing (OFCDM) wireless access, in order to achieve the maximum radio link capacity. Simulation results considering various propagation channel conditions elucidate that the antenna diversity combining method with Equal Gain Combining (EGC) subsequent to the despreading employing MMSE combining based on pilot symbol-assisted channel estimation and interference power estimation can decrease the required average received signal energy per bit-to-background noise power spectrum density ratio (Eb/N0) the most, taking into account the impact of the inter-code interference. Furthermore, we clarify that the required average received Eb/N0 for the average packet error rate of 10-2 employing the diversity combining scheme with EGC after despreading with MMSE combining is improved by approximately 0.3 dB compared to the diversity combining scheme with EGC before despreading with MMSE combining at the number of code-multiplexing of 24 for the spreading factor of 32 in a 24-path Rayleigh fading channel.

In this paper, we focus on an image encryption scheme based on a truncated Baker transformation. The truncated Baker transformation globally preserves the original dynamics of Baker transformation but incorporates a random local rotation operator between two neighbor elements in the mapping domain in order to keep a finite precision. It generates binary sequences (the dynamics of elements) which have statistically good features on ergodicity, mixing and chaotic properties. The image encryption scheme extended from the truncated Baker transformation efficiently shuffles the input gray level image satisfying fundamental conditions on confusion and diffusion required for image encryption schemes. However, this scheme uses many binary sequences and thus needs to keep a large volume of secret keys. In order to solve this problem we introduce Peano space-filling curve in this scheme, which remarkably reduce the key size and mapping iterations without deteriorating good shuffling properties attained by this scheme.

Scattering of a plane wave obliquely incident on a meteor trail is studied using the full wave treatment by treating the trail as a stratified column which has Gaussian radial electron distribution. Due to the coupling of the fields, the coupled equations have to be solved simultaneously. They are treated in matrix form, so the uncoupled and the coupled components can be distinguished. Based on the oblique scattering geometry, the effects of the variation of the communication range and the trail orientation are investigated. In the case of the variation of the communication range, results are in accordance with the approximate models but they are in contrast in the case of the variation of the trail orientation. Calculated waveforms are compared with the experimental echo shapes. It is found that they are in good agreement with each other. Furthermore, a duration comparison indicates that the electron line densities of most of the received signals are in the transition region.