This paper compares the BER performance of two types of pilot channel-based coherent Rake combining achievable by the use of weighted multi-slot averaging (WMSA) channel estimation filter in DS-CDMA transmission links. One is for the time-multiplexed pilot channel and the other is for the parallel pilot channel. The WMSA channel estimation filter weights and averages the received pilot over a period of several slots to improve the BER performance. We propose the WMSA channel estimation filters for time-multiplexed pilot and parallel pilot structures. Achievable BER performance under frequency-selective fading environments is computer simulated. The simulation results show that almost same BER performance can be achieved for both pilot channel structures when the same energy is allocated to the pilot.

The Future Public Land Mobile Telecommunication Systems (FPLMTS) standards have made it quite clear that in the near future, the capability in doing wireless data transmission will become necessary in order to make the tether-free use of multimedia applications possible. CDMA is considered the most appropriate and probable radio access method of FPLMTS for its high capacity and flexibility in accommodation of multimedia and variable rate users. In order to further increase the capacity of CDMA system, several techniques have been studied and proposed such as an interference canceller and adaptive array antenna. We propose the novel multi-user detection type interference cancellation technique named SRIC (Symbol Ranking type IC) in this paper. SRIC is very feasible for its small amount of operation compared with other multi-user detection type ICs and can be added to a base station with slight alteration according to the requirement of higher capacity. The performance of SRIC depends on the method of calculating the likelihood. We studied three methods. In order to reduce the operations, we tried to propose two more methods. We confirmed that SRIC can make the system capacity about three times greater than that of a conventional RAKE receiver. We also confirmed that SRIC can be reduce its operations very much at some sacrifice of their performance. There are nine variants of SRIC, which have a trade off between performance and amount of operation. We can choose one of them which is most fit to our requirement. The first operation of SRIC is common with that of a conventional RAKE receiver. Therefore, SRIC can be introduced to conventional systems afterwards by inserting the interference canceller block which functions replica generation, removal, and ranking between output of a RAKE receiver and FEC decoder.

For usage in fading environments, the idea of utilizing radio signal processing with software programmable devices promises greater flexibility and functionality. However, to realize these benefits very high performance DPSs and AD converters are required, especially for adaptive antennas with CDMA. One potential method of reducing the implementation complexity is to employ multicarrier (MC) modulation as it allows parallel signal processing in addition to its benefits in combating fading and ISI effects. This paper proposes a system utilizing MC DS/CDMA and a recursive adaptive array antenna processing algorithm for estimating the array response vector (array manifold) and hence the optimal weights. In order to evaluate this system performance results obtained through computer simulations are presented. The proposed MC system improves the accuracy of the direction-of-arrival (DOA) estimation of the signal by 2 degrees as compared with a single carrier system. It is also shown that the proposed adaptive array antenna algorithm for MC DS/CDMA reduces the number of iterations of the power method significantly and allows parallel processing of the adaptive algorithm.

A RAKE combiner based on a matched filter (MF) can be relatively easily implemented since the despread signal components that have propagated along different paths appear sequentially at the MF output. An important design problem is how to accurately select the paths having sufficiently large signal-to-noise power ratios (SNRs). This paper proposes a simple path selection algorithm that uses two selection thresholds. The first threshold is to select the paths that provide largest SNRs. However, as the total received signal power (sum of the signal powers of all paths) decreases, some of the selected paths become noisy. Therefore, we introduce a second threshold that discards the noisy or noise-only paths from among those selected by the first threshold. We apply the proposed path selection algorithm to a pilot symbol-assisted coherent RAKE combiner and find by computer simulations a near optimum set of the two thresholds in frequency selective multipath Rayleigh fading channels. Several power delay profile shapes are considered. The simulation results demonstrate that the MF-based RAKE combiner with the two selection thresholds can achieve a bit-error-rate (BER) performance close to the ideal case (i. e. , the paths to be used for RAKE combining are selected for each power delay profile such that the required signal energy per information bit-to-noise spectrum density ratio (Eb/N0) is minimized).

To enhance the anti-fading technique of direct sequence code division multiple access (DS/CDMA) schemes in land mobile radio communication systems, a two-dimensional RAKE reception (2D-RAKE) scheme in beam space digital beam forming (BS-DBF) antenna configuration is proposed. The proposed scheme is applied to cellular base stations where the received signals in the reverse link are relieved from multipath fading by means of enhanced RAKE combining in spacial and temporal domains. Fundamental performance in the reverse link under multipath fading environments is investigated by computer simulation applying a wideband propagation channel model.

We previously proposed a next generation cellular system for IMT-2000 based on wideband DS-CDMA with TDD scheme and have evaluated its performance by computer simulation, laboratory and field experiments. This paper presents the design concept of TDD-mode operation on wideband DS-CDMA systems. These systems employ almost the same techniques with a little difference as FDD-mode. We also present the schemes of the TDD-mode specific techniques such as fast cell search, transmission diversity and transmitter power control and show the evaluation results of them are effective. Performance can be improved by use of enhanced techniques such as interference cancellation and adaptive antenna array diversity.

The final closed-form expression of the bit error rate (BER) is presented for a DS-CDMA system using a maximal ratio combining (MRC) diversity in conjunction with simple channel coding over a Rician fading channel. The accuracy of the BER evaluated by this expression is verified through comparison with a semi-analytic simulation result. The effect of diversity order and channel coding on the bit error rate performance is also considered for typical multipath delay profiles with different Rician ratios.

A photorefractive ring resonator with self-pumped four-wave mixing (PRRR-SPFWM) in which the Cat mirror region and the four-wave mixing region are formed in a single photorefractive crystal is proposed, and the steady-state analysis of this unknown device is first performed. Since the backward pump beam is generated as a phase conjugate of the forward pump beam in the Cat mirror region, counterpropagation of both pump beams is spontaneously obtained. We analyze its oscillation intensities in steady state, and show that the threshold coupling strength of oscillation depends on the cavity mirror reflectivity and the reflectivity of the Cat mirror region. We also show interesting property of PRRR-SPFWM, the possibility to switch over between unidirectional and bidirectional oscillation by controlling the amplitude of coupling strength.

Testing for delay faults is very important in the verification of the timing behavior of digital circuits. When a circuit which is unable to operate at the desired clock speed is identified, it is necessary to locate the delay fault(s) affecting the circuit in order to remedy the situation. In this paper, we present a path-tracing method of multiple gate delay fault diagnosis in combinational circuits. We first present the basic rules for deducing suspected faults based on the multiple gate delay fault assumption. Next, in order to improve diagnostic resolution, we introduce rules for deducing non-existent faults based on the fault-free responses at the primary outputs. Using these rules, we present the detailed method for diagnosing multiple delay faults based on paths sensitized by test-pairs generated for marginal delays and gate delay faults [7]. Finally, we present results obtained from experiments on the ISCAS '85 benchmark circuits. The experimental results show the effectiveness of our method.

We have specified typical fabrication defects of the current injection logic gates with four Josephson junctions (4JL gates), and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that current testing may possibly achieve a high defect coverage while logic testing cannot detect almost half defects.

Cellular automata (CA) implementations are expected as potential test-pattern generators (TPGs) for Built-In Self-Testing of VLSI circuits, in which highly random parallel patterns ought to be generated with simple hardware. Objective here is to design one-dimensional, binary, and linear CA implementations with cyclic boundary conditions that can operate on maximum length of period. To provide maximum period of operations, it is necessary to bring some irregularities into the configurations. It is also expected for TPGs to make maximum or sufficiently long period of operations to prevent re-initialization. Our approach is to generate transition matrices based on fast parallel implementations of LFSRs which have trinomials as characteristic polynomials and then to modify the diagonal components. Some notable properties of diagonal vectors were observed.

In this paper, we propose several novel methods to decrease propagation error for multiple access interference cancellation techniques in asynchronous DS/CDMA. To increase spectral efficiency, the system wherein transmitting signal power of each user is assigned with exponential law and multiple access interference successive cancellation is used in the receiver has been discussed. However, when the number of active users is increased, propagation error occurs in the receiver. Thus, the improvement effect of spectral efficiency in the system has been degraded. In this paper, we propose novel methods to decrease these propagation errors for the system. These novel methods are quasi-maximum likelihood method that means maximum likelihood in considering the signal of the next user when the signal of the arbitrary user is demodulated, feedback method that means the demodulation error of the stronger users in transmitting signal power is estimated after several users, demodulations and the error is corrected, and combination method that is a combination of quasi-maximum likelihood method and feedback method. And we evaluate their performances by computer simulation and show that the combination method is effective for the reduction of the propagation error.

We have studied the basic optical and physical characteristics of polymeric optical waveguide films with S-shaped waveguides and 45 mirrors applied as multimode optical interconnection components. The core and cladding of the waveguide films were made of deuterated-polymethylmethacrylate (d-PMMA) and UV-cured resin, respectively. We evaluated the insertion losses of the waveguides, the crosstalk and the 45-mirror losses in these waveguide films and demonstrated that they have low propagation loss. The shrinkage and thermal expansion of the polymeric optical waveguide films are also discussed because of the interest in improving module packaging.

We have improved the optical beam induced resistance change (OBIRCH) system so as to detect (1) a current path as small as 10-50 µA from the rear side of a chip, (2) current paths in silicide lines as narrow as 0. 2 µm, (3) high-resistance Ti-depleted polysilicon regions in 0. 2 µm wide silicide lines, and (4) high-resistance amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm 5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.

This paper presents a new methodology for diagnosing transistor leakage faults in a CMOS circuit by using both IDDQ and logic value information. A hierarchical procedure is used to identify and delete impossible fault candidates efficiently and a procedure is employed to generate diagnostic tests for improving diagnostic resolution. A novel approach for handling the intermediate output voltage of a faulty gate is used in new methods for fault simulation and diagnostic test generation based on primary output values. Experimental results on ISCAS85 circuits show the effectiveness of the proposed methodology.

This paper presents a test generation method for sequential circuits under IDDQ testing environment and the identification of untestable faults based on the information of illegal states. We consider a short between two signal lines, a short within one gate and a short between two nodes in different gates. The proposed test generation method consists of two techniques. First technique is to use weighted random vectors, and second technique is to use test generator for stuck-at faults. By using the two techniques together, high fault coverage and short computational time can be achieved. Finally experimental results for ISCAS89 benchmark circuits are presented.

Three types of ternary decision diagrams (TDDs) are considered: AND -TDDs, EXOR-TDDs, and Kleene-TDDs. Kleene-TDDs are useful for logic simulation in the presence of unknown inputs. Let N(BDD:f), N(AND-TDD:f), and N(EXOR-TDD:f) be the number of non-terminal nodes in the BDD, the AND-TDD, and the EXOR-TDD for f, respectively. Let N(Kleene-TDD:) be the number of non-terminal nodes in the Kleene -TDD for , where is the regular ternary function corresponding to f. Then N(BDD:f) N(TDD:f). For parity functions, N(BDD:f)=N(AND-TDD:f)=N(EXOR-TDD:f)=N(Kleene-TDD:). For unate functions,N(BDD:f)=N(AND-TDD:f). The sizes of Kleene-TDDs are O(3n/n), and O(n3) for arbitrary functions, and symmetric functions, respectively. There exist a 2n-variable function, where Kleene-TDDs require O(n) nodes with the best order, while O(3n) nodes in the worst order.

This paper presents an acceleration of test points selection for circuits designed by a full-scan based BIST scheme. In order to accelerate the test points selection based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed techniques and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).

We present a high-level synthesis scheme that considers weak testability of generated register-transfer level (RTL) data paths, as well as their area and performance. The weak testability, proposed in our previous work, is a testability measure of RTL data paths for non-scan design. In our scheme, we first extract a condition on resource sharing sufficient for weak testability from a data flow graph before synthesis, and treat the condition as design objectives in the following synthesis tasks. We propose heuristic synthesis algorithms which optimize area and the design objectives under the performance constraint.

We fabricated a tunable and polarization-insensitive arrayed-waveguide grating (AWG) 1616 multiplexer that operates around the wavelength of 1. 55 µm using fluorinated polyimides. The wavelength channel spacing was 0. 8 nm, and the 3-dB passband width was 0. 26 nm. The insertion loss at each channel was from 8 to 12 dB, and the crosstalk was less than -28 dB. The transmission pass wavelength was tuned over a wide range of 6 nm by heating from 24 to 64. The slope of the temperature dependence of the pass wavelength was -0. 15 nm/, which is ten times that of a silica-based multiplexer. Polarization-insensitivity was achieved by fabricating a film AWG multiplexer, which was formed by removing the silicon substrate and annealing at 350. The polarization-dependent wavelength shift was smaller than the spectrum analyzers wavelength resolution of 0. 1 nm.