A practical structural representation of a segmented image is presented. The practicalness is defined according to whether or not the representation can be directly generated from its corresponding segmented image. Two structural representations have been proposed in the literature. They are hierarchical structure and relational graph. Because they are defined totally on the basis of human perception, neither of the representations can be directly generated from the corresponding segmented image. The structural representation described in this paper, however, is based on the relations among pattern primitives and generated by applying some human-oriented constraints.

This paper designs recursive least-squares fixed-point smoother and filter, which use the observed value, the probability that the signal exists, and the covariance information relevant to the signal and observation noises, on the estimation problem associated with the uncertain observations in linear continuous-time systems.

This paper illustrates activities and accomplishments being made by DAVIC, a non-profit organization pushing forward its open, international, cross-industry standards for audio-visual information systems, of which video-on-demand is the representative. Core technologies selected in its firstly published specifications and their interoperability aspects are summarized here. Preliminary results in our interoperability testing are also shown. Finally, we touch upon the coming work plan of DAVIC which covers wider range of access network capabilities and service domains, e.g. internet.

A structural active-object system (SAOS) is a transition-based object-oriented system suitable for rapid development of hardware logic simulators. A SAOS consists of a collection of interacting structural active objects (SAOs), whose behaviors are determined by the transition statements provided in their class definitions. Furthermore, SAOs can be structurally and hierarchically composed from their component SAOs like hardware components. These features allow SAOs to model components for circuit simulation more naturally than passive objects used in ordinary object-oriented programming. Also, we can easily create new kinds of components by using the inheritance mechanism. Executions of transition statements may be event-and/or time-driven, and hence digital, analog, and mixed-mode simulation is possible. Prototype simulation programs with graphical user interfaces have been developed as SAOS programs for digital, analog, and mixed-mode circuit simulation.

The MU radar of Japan is one of important candidates for providing accurate ground truth for the TRMM precipitation radar. It can provide the dropsize distribution data together with the background atmospheric wind data with high accuracy and high spatial resolution. Special observation scheme developed for TRMM validation using the MU radar is described, and preliminary results from its test experiment are shown. The high-resolution MU radar data are also used in numerical simulations to validate the rain retrieval algorithm for the TRMM PR data analysis. Among known sources of errors in the rain retrieval, the vertical variability of the dropsize distribution and the partial beam-filling effect are examined in terms of their significance with numerical simulations based on the MU radar data. It is shown that these factors may seriously affect the accuracy of the TRMM rain retrieval, and that it is necessary to establish statistical means for compensation. However, suggested means to improve the conventional α-adjustment method require careful treatment so that they do not introduce new sources of errors.

We have fabricated a new analog memory for integrated artificial neural networks. Several attempts have been made to develop a linear characteristics of floating-gate analog memorys with feedback circuits. The learning chip has to have a large number of learning control circuit. In this paper, we propose a new analog memory SDAM with three cascaded TFTs. The new analog memory has a simple design, a small area occupancy, a fast switching speed and an accurate linearity. To improve accurate linearity, we propose a new chargetransfer process. The device has a tunnel junction (poly-Si/poly-Si oxide/poly-Si sandwich structure), a thin-film transistor, two capacitors, and a floating-gate MOSFET. The diffusion of the charges injected through the tunnel junction are controlled by a source follower operation of a thin film transistor (TFT). The proposed operation is possible that the amounts of transferred charges are constant independent of the charges in storage capacitor.

When we use a telephone-handset, the frequency response of the telephone-earphone becomes degraded because of the leak through the slit between the ear and the earphone. Consequently, it is very important to establish the design method of the telephone-handset which reduces the effect of leak. No one has tried to design the telephone-handset to reduce the effect. We are the only ones to have proposed an automatic design method by nonlinear optimization techniques. However, this method gives only one set of the acoustic parameters aiming at a certain specific target frequency response, and therefore lacks flexibility in the actual design problem. On the other hand, the design method proposed in this paper, which uses Monte-Carlo method, gives an infinite number of sets of acoustic parameters that realize infinite frequency responses within the target allowable region. As these infinite number of sets become directly the design ranges of acoustic parameters, the proposed method has the flexibility that any set of the acoustic parameters belonging to the design ranges guarantees the corresponding response to be within the target allowable region, and at the same time reduces the effect of leak. This flexibility is advantageous to the actual design problem.

In this paper, a simple method to investigate the dynamics of continuous-time neural networks based on the force (kinetic vector) derived from the equation of motion for neural networks instead of the energy function of the system has been described. The number of equilibrium points and limit cycles of one-dimensional neural networks with the asymmetric cyclic connection matrix has been investigated experimently by this method. Some types of equilibrium points and limit cycles have been theoretically analyzed. The relations between the properties of limit cycles and the number of connections also have been discussed.

In this paper, a super-resolution method based on the Discrete Cosine Transform (DCT) is proposed for a signal with some frequency damage. If the damage process can be modeled as linear convolutoin with a type 1 linear phase FIR filter, it is shown that some DCT coefficients of the damaged signal are the same as those of the original signal except for the DCT coefficients corresponding to the frequency damage. From this investigation, the proposed method is provided for the DCTs with four types as expanding the super-resolution method based on the Discrete Fourier Transform (DFT). In addition,two magnification approaches based on the proposed method are described to improve the conventional approach.

In this paper, a post-layout optimization technique for power dissipation and timing of cell-based Bipolar ECL LSIs is proposed. An ECL LSI can operate at a frequency of a few GHz but the power dissipation is very high compared to CMOS LSIs, which makes the systems using ECL quite expensive. Therefore it is crucial to develop of CAD techniques that minimize the power dissipation of an ECL LSI without decreasing its performance. To begin with, power and delay models of an ECL gate are presented as functions of its switching current. The power dissipation is a linear function of the switching current and the delay time is its hyperbolic function. These functions are obtained considering the post-layout interconnect capacitance and resistance to make the optimization results accurate enough. Using the delay model, a set of timing constraints specifying the max/min cell delay and the clock skew are extracted. This set of constraints in then given to a nonlinear programming package. The objective functions are clock skew time, the clock cycle time and the power dissipation, which are optimized in this order. With the minimum delay and hold constraints, the problem is not convex so that conventional convex programming approach cannot be used. As a result of the optimization, the switching currents for cells are obtained. These are realized within cells by regulating programmable resistors", which is a special feature of our ECL cell library. Since the above optimization is carried out after the placement and routing of the circuit, it can take accurate delay and power estimation into consideration. Experimental results show more than 40% power reductions for circuits including a real communication system chip, compared to the max power versions. The clock cycle time was maintained or even made faster due to the efficient clock skew optimization.

This paper describes the results obtained of a prototype system, VeriProc/1, based on an algorithm we first presented in [13] which can prove the correctness of pipelined processors automatically without pipeline invariant, human interaction, or additional information. No timing relations such as an abstract function or β-relation is required. The only information required is to specify the location of the selectors in the design. The performance is independent of not only data width but also memory size. Detailed analysis of CPU time is presented. Further, don't-care forcing using additional data easily prepared by the user can improve performance.

In general, a learning machine will behave better as the number of training examples increases. It is important to know how fast and how well the behavior is improved. The average prediction error, the average of the probability that the trained machine mispredicts the output signal, is one of the most popular criteria to see the behavior. However, it is not easy to evaluate the average prediction error even in the simplest case, that is, the linear dichotomy (perceptron) case. When a continuous deterministic dichotomy machine is trained by t examples of input-output pairs produced from a realizable teacher, these examples limits the region of the parameter space which includes the true parameter. Any parameter in the region can explain the input-output behaviors of the examples. Such a region, celled the admissible region, forms in general a (curved) polyhedron in the parameter space, and it becomes smaller and smaller as the number of examples increases. The present paper studies the shape and volume of the admissible region. We use the stochastic geometrical approach to this problem. We have studied the stochastic geometrical features of the admissible region using the fact that it is dual to the convex hull the examples make in the example space. Since the admissible region is related to the average prediction error of the linear dichotomy, we derived the new upper and lower bounds of the average prediction error.

We propose a speech recognition method using fusion of auditory and visual information for accurate speech recognition. Since we use both auditory information and visual information, we can perform speech recognition more accurately in comparison with the case of either auditory information or visual information. After processing each information by HMM, they are fused by linear combination with weight coefficient. We performed experiments and confirmed the validity of the proposed method.

The effects of α-particle-induced parasitic bipolar current on soft errors in submicron 6-transistor SOI SRAMs were numericaly studied. It was shown that the bipolar current induces soft errors and that there exists a critical quantity which determines the soft error occurrence in the SOI SRAMs. Simulated soft error rates were in the same order as those for bulk SRAMs.

Multimedia communications, fast growing industry in the world and in Korea, require advanced technology in network, computer, device, and application software. Korean government and industries prepare for this huge opportunity by commitment to national R&D programs. While investing heavily on present multimedia products, private companies also support R&D on future multimedia technologies. This paper surveys key R&D efforts in Korea by programs and organizations.

AlGaAs/GaAs power HBTs for digital cellular phones have been developed. A three-dimensional thermal analysis taking the local-temperature dependence of the collector current into account was applied to the thermal design of the HBTs. The HBTs were fabricated using the hetero-guardring fully selfaligned transistor technique. The HBT with 220µm2 60 emitters produced a 31.7 dBm CW-output power and 46% poweradded efficiency with an adjacent channel leakage power of -49 dBc at the 50kHz offset bands for a 948 MHz π/4-shifted QPSK modulated signal at a low collector-emitter voltage of 3V. Through comparison with the conventional GaAs power FETs, it has been shown that AlGaAs/GaAs power HBTs have a great advantage in reducing the chip size.

A 1.9GHz direct conversion receiver(DCR) chip which integrates an LNA, I/Q mixers(MIX), active lowpass filters(LDF) and variable gain amplifiers(VGA) was fabricated. Because the DCR for QPSK modulation systems is sensitive to the 2nd-order nonlinearity, linearization techniques are adopted in MIX and LPF. The DCR chip was fabricated using a BiCMOS process, and the die size is 5.1 mm by 5.1mm. The chip can operate from 2.7 V supply voltage and consumes 165mW when all the functions are activated. Suppression of local signal radiation and the 2nd-order distortion indicate the feasibility of Si-based DCR for QPSK modulation systems such as PHS.

Asynchronous Transfer Mode (ATM) is a promised bearer transmission service for high speed multimedia LAN. Recently, high speed multimedia ATM LAN products have been available. Therefore, in order to interconnect them, the multimedia backbone LAN, which has the expandable high throughput over 10Gbps, supporting multicast, multi-QoS, and many interfaces including 622 Mbps, will be widely required. In this paper, the VLSI oriented input and output buffered switch architecture is proposed as the hardware architecture for multimedia backbone switch node. This paper describes that the chip set consisting of four VLSIs, that is, the switch element, the switch access, the distributor/arbiter, and the multiplexer/demultiplexer, can realize the backbone switch core, and the main specifications required to each VLSI are derived.

Handwritten character recognition has been increasing its importance and has been expanding its application areas such as office automation, postal service automation, automatic data entry to computers, etc. It is challenging to develop a handwritten character recognition system with high processing speed, high performance, and high portability, because there is a trade-off among them. In current technology, it is difficult to attain high performance and high processing speed at the same time with single algorithms, and therefore, we need to find an efficient way of combination of multiple algorithms. We present an engineering solution to this problem. The system is based on multi-stage strategy as a whole: The first stage is a simple, fast, and reliable recognition algorithm with low substitution-error rate, and data of high quality are recognized in this stage, whereas sloppily written or degraded data are rejected and sent out to the second stage. The second stage is composed of a sophisticated structural pattern classifier and a pattern matching classifier, and these two complementary algorithms run in parallel (multiple expert approach). We demonstrate the performance of the completed system by experiments using real data.

Most conventional methods used in character recognition extract geometrical features, such as stroke direction and connectivity, and compare them with reference patterns in a stored dictionary. Unfortunately, geometrical features are easily degraded by blurs and stains, and by the graphical designs such as used in Japanese newspaper headlines. This noise must be removed before recognition commences, but no preprocessing method is perfectly accurate. This paper proposes a method for recognizing degraded characters as well as characters printed on graphical designs. This method extracts features from binary images, and a new similarity measure, the complementary similarity measure, is used as a discriminant function; it compares the similarity and dissimilarity of binary patterns with reference dictionary patterns. Experiments are conducted using the standard character database ETL-2, which consists of machine-printed Kanji, Hiragana, Katakana, alphanumeric, and special characters. The results show that our method is much more robust against noise than the conventional geometrical-feature method. It also achieves high recognition rates of over 97% for characters with textured foregrounds, over 99% for characters with textured backgrounds, over 98% for outline fonts and over 99% for reverse contrast characters. The experiments for recognizing both the fontstyles and character category show that it also achieves high recognition rates against noise.