In this paper, a new algorithm for selection of candidates for handwritten character recognition is presented. Since we adopt the concept of the marginal radius to examine the confidence of candidates, the evaluation function is required to describe the pattern distribution correctly. For this reason, we propose Simplified Mahalanobis distance and observe its behavior by simulation. In the proposed algorithm, first, for each character, two types of feature regions (multi-dimensional one and one-dimensional one) are estimated from training samples statistically. Then, by referring to the feature regions, candidates are selected and verified. Using two types of feature regions is a principal characteristic of our method. If parameters are estimated accurately, the multi-dimensional feature region is extremely effective for character recognition. But generally, estimation errors in parameters occur, especially with a small number of sample patterns. Although the recognition ability of one-dimensional feature region is not so high, it can express the distribution comparatively precisely in one-dimensional space. By combining these feature regions, they will work concurrently to overcome the defects of each other. The effectiveness of the method is shown with the results of experiments.

In this paper, authors propose a linear array antenna using two bifilar helical antenna elements placed along the helix axis to reduce beam direction movement according to frequency change. The beam direction movement of this proposed array antenna is smaller than that of a conventional bifilar helical antenna. Also, the gain of this proposed array antenna is higher than that of the conventional helical antenna for a cross point angle of radiation patterns at the different transmit and receive(Tx and Rx) frequencies. The conventional helical antenna is suitable for vehicle antennas in mobile satellite communication systems such as the MSAT system because it owns circularly polarized omni-directional radiation pattern and its thin pole form. However, this antenna has a disadvantage that the beam direction in an elevation plane moves according to frequency change. In the proposed array antenna, the beam direction movement is about 9 smaller than that of the conventional bifilar helical antenna on condition that antenna total length is 4.83 λ0, antenna diameter is 0.12 λ0, and frequency change is from 0.957f0 to 1.043f0(f0 is center frequency and λ0 is free space wavelength at f0). Also, the Tx and Rx gains of this proposed array antenna at the cross point angle between Tx and Rx beams are about 2 dB higher than that of the conventional bifilar helical antenna on the same condition.

This paper proposes a new approach for inputting handwritten Distribution Facility Drawings (DFD) and their maps into a computer automatically by using the Facility Management Database (FMD). Our recognition method makes use of external information for drawing/map recognition. It identifies each electric-pole symbol and support cable symbol on drawings simply by consulting the FMD. Other symbols such as transformers and electric wires can be placed on drawings automatically. In this positioning of graphic symbols, we present an automatic adjustment method of a symbol's position on the latest digital maps. When a contradiction is unsolved due to an inconsistency between the content of the DFD and the FMD, the system requests a manual feedback from the operator. Furthermore, it uses the distribution network of the DFD to recognize the street lines on the maps which aren't computerized. This can drastically reduce the cost for computerizing drawings and maps.

A miniature transceiver, including highly integrated MMIC front-end, for 1.9 GHz band personal handy phone system(PHS) has been developed. The terminal, adopting direct conversion transmitter and receiver technology, consists of four high-density RF circuit modules and a digital signal processing LSI with 2.7 V power supply. The four functional modules are a power amplifier, a transmitter,a receiver, and a frequency synthesizer. Each functional module includes one IC chip and passive LCR components connected with solder bumps on module substrate. The experimental miniature PHS handset has been fabricated to verify the design concepts of the miniature transceiver. The total volume of the developed PHS terminal is 60cc, including the 12cc front-end which comprises the four RF functional circuit modules. The air interface connection with the PHS base station simulator has been confirmed.

An effect of source harmonic tuning on linearity of power GaAs FET's under class AB operation is demonstrated. To improve efficiency of the power amplifiers, GaAs FET's are often poerated under class AB condition. Due to lower bias current, a class AB amplifier begins to show nonlinearity at lower input power comparing with class A operation, and as the power level of the input signal increases, however, an output power sometimes increases abruptly. From nonlinear circuit simulation, we have found this phenomenon is occurred by the distortion in gate RF voltage, and by suppressing even-order harmonics in the input circuit of GaAs FET, class AB amplifiers can be effectively linearized. In this paper, we show the condition for improving the linearity of power CaAs FET's under class AB operation by the source harmonic tuning technique.

This paper presents a combinatiorial characterization of broadcast authentication in which a transmitter broadcasts v messages e1(s), , ev(s) to authenticate a source state s to all n receivers so that any k receivers cannot cheat any other receivers, where ei is a key. Suppose that each receiver has l keys. First, we prove that k < l if v < n. Then we show an upper bound of n such that n v(v - 1)/l(l - 1) for k = l - 1 and n /+ for k < l - 1. Further, a scheme for k = 1 - 1 which meets the upper bound is presented by using a BIBD and a scheme for k < l - 1 such than n = / is presented by using a Steiner system. Some other efficient schemes are also presented.

This letter proposes ALPEN, a simple, flexible and cost effective ATM-WAN architecture that emulates multiple ATM-layer protocols at the edge nodes. Any new ATM-layer protocol can be easily implemented by modifying only the edge nodes. The transit network is simple and independent of the protocols emulated, and ALPEN has a short response time. It is very suitable for implementing multimedia ATM networks.

Ultrashallow p-type layers have been formed using an one-wafer type reactor for rapid vapor-phase doping (RVD) with lamp annealing system. Bipolar and MOS transistors were fabricated using the system for the first time. The process includes the injection of the B2H6 diffusion source gas with hydrogen carrier gas at room temperature and rapid thermal annealing using lamps. Ultrashallow boron doping was achieved at 900 for 60 seconds; that is, the junction depths were less the 60 nm with a peak boron concentration of between 1019 and 1020 cm-3. The sheet boron concentrations is controlled by adjusting the flow rate of B2H6. To show the potential of the process, bipolar and MOS transistors were fabricated. The base regions of conventional bipolar transistors were formed by rapid vapor-phase doping. Transistors with 20-nm base and emitter were fabricated and they showed current gain of 150. Shallow source and drain of PMOS transistors were also formed. The threshold voltage roll-off was suppressed down to gate length of 0.22 µm, while devices with BF2-implanted source and drain showed the roll-off below 0.5 µm. Devices with RVD-source and drain thus have drain current 1.5 times higher than those with BF2 ion implantation. RVD provides both good short-channel characteristics and high current drivability.

A decision circuit with a function of detecting the phase difference between input data and clock signal is presented. Direct coupled FET logic (DCFL) was used for basic gates. The circuit architecture was chosen to be suitable for DCFL. Novel circuit technologies were adopted to the phase detectors. In GaAs/AlGaAs pseudomorphic inverted HEMT's were used for fabrication. The decision circuit showed a wide phase margin of 288 degrees and small decision ambiguity of 27 mVpp up to 10 Gb/s. Linear and wide-range phase detection was achieved as well as an ability to compensate the variation of transition density, input bias and temperature.

Protective layers in AC plasma display panels (PDP) are usually formed by vacuum vapor deposition or sputtering. It is important to study the protective MgO layer by means of screen-printing for fabricating a large size PDP and reducing its cost. With the objectives of enlarging the panel size and reducing cost, we studied the fabrication of the protective MgO layer by means of screen-printing. In this study, we succeeded in lowering the drive voltage by using a MgO powder prepared by vapor phase oxidation instead of conventional decomposition of the magnesium salt. Further, by adding a MgO liquid binder, we attained a good luminous efficiency twice as high as that attained with a sputtered protective layer and lowered the drive voltage. When this protective layer was combined with He-Xe gas enclosure, the half-life of luminance was 5,000 hours. With Ne-Xe gas, the luminance deteriorated no more than 40% after 5,000 hours. A screen-printed protective MgO layer containing no MgO liquid binder showed a short half-life of 800 hours even with the use of Ne-Xe gas. In this case, the discharge voltage changed greatly and some cells did not discharge. It is concluded that the combination of an ultrafine MgO powder prepared by vapor phase oxidation and a MgO liquid binder can clear the way for making AC PDPs with a long lifetime, high efficiency, and low voltage a practical reality.

GaAs 10 Gb/s 64:1 Multiplexer/Demultiplexer chip sets have been successfully developed. The 64-bit 156 Mb/s parallel data output or input of these chip sets can be directly connected to CMOS LSIs. These chip sets consist of a 10Gb/s 4: 1 MUX IC, a 10 Gb/s 1: 4 DEMUX IC, four 2.5 Gb/s 16: 1 MUX LSIs and four 2.5 Gb/s 1: 16 DEMUX LSIs. This multi-chip construction is adopted for low power dissipation and high yield. The basic circuit employed in the 10 Gb/s4: 1 MUX/DEMUX ICs is an SCFL circuit using 0.4 µm-gate FETs with a power supply of -5.2 V, and that in 2.5 Gb/s 16: 1 MUX/DEMUX LSIs is a DCFL circuit using 0.6 µm-gate FETs with a power supply of -2.0 V. These chip sets have functions for synchronization among these ICs and to enable bit shift to make the system design easier. In the 10 Gb/s 4: 1 MUX IC, a timing adjuster is adopted. This timing adjuster can delay the timing of the most critical path by 50 ps. Even if the delay times are out of order due to fluctuations in process, temperature, power supply voltage and other factors, this timing can be revised and the 4: 1 MUX IC can operate at 10 Gb/s. Furthermore, a 48-pin quad flat package for 10 Gb/s 4: 1 MUX/DEMUX ICs has been newly developed. The measured insertion loss is 1.7 dB (at 10 GHz), and the isolation is less than -20 dB (at 10 GHz). These values are sufficient in practical usage. Measurements of these chip sets show desirable performance at the target 10 Gb/s. The power dissipations of the 64: 1 MUX/DEMUX chip sets are 10.3 W and 8.2 W, respectively. These chip sets is expected to contribute to high speed telecommunication systems.

We present a 64-b adder having a 2.6-ns delay time at 3.3 V power supply within 0.27 mm2 using 0.5-µm CMOS technology. We derived our adder design from architectural level considerations. The considerations include not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. As a result, a 64-b adder, (56-b Carry Look-ahead Adder(CLA) +8-b Carry Select Adder (CSA)), was designed. In this design, a new carry select scheme called Modified Carry Select (MCS) is also proposed.

It is demonstrated with the Berlekamp-Massey shift-register synthesis algorithm that the linear complexity value of binary complementary sequences is at least 3/4 of the sequence length. For some sequence pairs the linear complexity value can be even 0.98 times the sequence length. In the light of these results strongly non-linear complementary sequences are considered suitable for information security applications employing the spread-spectrum (SS) technique.

The coupling response of an external transient electromagnetic field to a transmission line is considered. An experiment has been conducted to verify the line equations for a transmission line excited externally by a transient near field. The model field is generated by a monopole antenna installed in the vicinity of the transmission line and driven by a step waveform. The waveform is analyzed into discrete spectrum components using a Fourier transform. The frequency-domain field components affecting the transmission line are estimated by the moment method, and then the induced frequency-domain voltage at the terminal load is converted into a time-domain voltage using an inverse Fourier transform. Comparison between the measured and the computed values provides verification of the line equations. The coupling mechanism is discussed from the experimental results. It seems equivalently that the transmission line picks up the field, generated at the feed point and the top point of the monopole antenna, at both terminal ends.

A model for the floating point adder/subtractor which can perform rounding and addition/subtraction operations in parallel is presented. The major requirements and structure to achieve this goal are described and algebraically verified. Processing flow of the conventional floating point addition/subtraction operation consists of alignment, addition/subtraction, normalization, and rounding stages. In general, the rounding stage requires a high speed adder for increment, increasing the overall execution time and occupying a large amount of chip area. Furthermore, it accompanies additional execution time and hardware logics for renormalization stage which may occur by an overflow from the rounding operation. A floating adder/subtractor performing addition/subtraction and IEEE rounding in parallel is designed by optimizing the operational flow of floating point addition/subtraction operation. The floating point adder/subtractor presented does not require any additional execution time nor any high speed adder for rounding operation. In addition, the renormalization step is not required because the rounding step is performed prior to the normalization operation. Thus, performance improvement and cost-effective design can be achieved by this approach.

A directed graph G = (V,E) is called the n-rotator graph if V = {a1a2an|a1a2an is a permutation of 1,2,,n} and E = {(a1a2an,b1b2bn)| for some 2 i n, b1b2bn = a2aia1ai+1an}. We show that for any pair of distinct nodes in the n-rotator graph, we can construct n - 1 disjoint paths, each length < 2n, connecting the two nodes. We propose a nonadaptive fault-tolerant file transmission algorithm which uses these disjoint paths. Then the probabilistic analysis of its reliability is given.

In anonymous survey, statistical information by attributes of respondents -such as his gender, age or adress-plays an important role in the interpretation of data. However, giving away all his attributes may cause privacy problem. That is, gathering many attributes may help identifying specifically who responded to the anonymous survey. In this paper, we propose a protocol executed among several `entities in charge' in order to compute statistical information for surveys. The advantage of adopting this protocol is that it does not release extra information of attributes on calculating statistical results. We can show that this protocol is a secure computation in the sense of Micali-Rogaway if played by semi-honest entities. We furthurly give a protocol with zero-knowledge proofs to ensure that the entities are indeed semi-honest.

With increases in the speed of semiconductor devices and integrated circuits, the importance of internal testing with sufficient temporal resolution has been growing. This paper describes recently established electro-optic testing technologies based on pulse lasers and electro-optic crystal probes. Practicability, limitation and future issues are discussed.

A high speed and low power consumption SCFL circuit design with low supply voltage is proposed. Focusing on the relationship between logic swing and supply voltage, the lower limit for the supply voltage is presented. Theoretical analysis and circuit simulation indicates that the logic swing needs to be optimized to maintain high average gm within the swing. An SCFL D-FF fabricated using a 0.25 µm n-AlGaAs/i-InGaAs HJFET process operates at up to 10 Gbps with power consumption as low as 19 mW at a supply voltage of 1.3 V.

A calibrating analog-to digital (A/D) converter employing a T-Model neural network is described. The T-Model neural-based A/D converter architecure is presented with particular emphasis on the elimination of local minimum of the Hopfield neural network. Furthermore, a teacher forcing algorithm is presented and used to synthesize the A/D converter and correct errors of the converter due to offset and device mismatch. An experimental A/D converter using standard 5-µm CMOS discrete IC circuits demonstrates high-performance analog-to-digital conversion and calibrating.