In order to improve the anomaly detection efficiency of network traffic, firstly, the model is established for network flows based on complex networks. Aiming at the uncertainty and fuzziness between network traffic characteristics and network states, the deviation extent is measured from the normal network state using deviation interval uniformly, and the intuitionistic fuzzy sets (IFSs) are established for the various characteristics on the network model that the membership degree, non-membership degree and hesitation margin of the IFSs are used to quantify the ownership of values to be tested and the corresponding network state. Then, the knowledge measure (KM) is introduced into the intuitionistic fuzzy weighted geometry (IFWGω) to weight the results of IFSs corresponding to the same network state with different characteristics together to detect network anomaly comprehensively. Finally, experiments are carried out on different network traffic datasets to analyze the evaluation indicators of network characteristics by our method, and compare with other existing anomaly detection methods. The experimental results demonstrate that the changes of various network characteristics are inconsistent under abnormal attack, and the accuracy of anomaly detection results obtained by our method is higher, verifying our method has a better detection performance.

Solar power is the most widely used renewable energy source, which reduces pollution consequences from using conventional fossil fuels. However, supplying stable power from solar power generation remains challenging because it is difficult to forecast power generation. Accurate prediction of solar power generation would allow effective control of the amount of electricity stored in batteries, leading in a stable supply of electricity. Although the number of power plants is increasing, building a solar power prediction model for a newly constructed power plant usually requires collecting a new training dataset for the new power plant, which takes time to collect a sufficient amount of data. This paper aims to develop a highly accurate solar power prediction model for multiple power plants available for both new and existing power plants. The proposed method trains the model on existing multiple power plants to generate a general prediction model, and then uses it for a new power plant while waiting for the data to be collected. In addition, the proposed method tunes the general prediction model on the newly collected dataset and improves the accuracy for the new power plant. We evaluated the proposed method on 55 power plants in Japan with the dataset collected for two and a half years. As a result, the pre-trained models of our proposed method significantly reduces the average RMSE of the baseline method by 73.19%. This indicates that the model can generalize over multiple power plants, and training using datasets from other power plants is effective in reducing the RMSE. Fine-tuning the pre-trained model further reduces the RMSE by 8.12%.

This paper introduces a deep reinforcement learning approach to solve the virtual network function scheduling problem in dynamic scenarios. We formulate an integer linear programming model for the problem in static scenarios. In dynamic scenarios, we define the state, action, and reward to form the learning approach. The learning agents are applied with the asynchronous advantage actor-critic algorithm. We assign a master agent and several worker agents to each network function virtualization node in the problem. The worker agents work in parallel to help the master agent make decision. We compare the introduced approach with existing approaches by applying them in simulated environments. The existing approaches include three greedy approaches, a simulated annealing approach, and an integer linear programming approach. The numerical results show that the introduced deep reinforcement learning approach improves the performance by 6-27% in our examined cases.

In this paper, we investigate the sum rate (SR) maximization problem for downlink cooperative non-orthogonal multiple access (C-NOMA) system under in-phase and quadrature-phase (IQ) imbalance at the base station (BS) and destination. The BS communicates with users by a half-duplex amplified-and-forward (HD-AF) relay under imperfect IQ imbalance. The sum rate maximization problem is formulated as a non-convex optimization with the quality of service (QoS) constraint for each user. We first use the variable substitution method to transform the non-convex SR maximization problem into an equivalent problem. Then, a joint power and rate allocation algorithm is proposed based on successive convex approximation (SCA) to maximize the SR of the systems. Simulation results verify that the algorithm can improve the SR of the C-NOMA compared with the cooperative orthogonal multiple access (C-OMA) scheme.

In this paper, we investigate the Access Point (AP) selection problem in Cell-Free Massive multiple-input multiple-output (MIMO) system. Firstly, we add a connecting coefficient to the uplink data transmission model. Then, the problem of AP selection is formulated as a discrete combinatorial optimization problem which can be dealt with by the particle swarm algorithm. However, when the number of optimization variables is large, the search efficiency of the traditional particle swarm algorithm will be significantly reduced. Then, we propose an ‘user-centric’ cooperative coevolution scheme which includes the proposed probability-based particle evolution strategy and random-sampling-based particle evaluation mechanism to deal with the search efficiency problem. Simulation results show that proposed algorithm has better performance than other existing algorithms.

In this paper, user set selection in the allocation sequences of round-robin (RR) scheduling for distributed antenna transmission with block diagonalization (BD) pre-coding is proposed. In prior research, the initial phase selection of user equipment allocation sequences in RR scheduling has been investigated. The performance of the proposed RR scheduling is inferior to that of proportional fair (PF) scheduling under severe intra-cell interference. In this paper, the multi-input multi-output technology with BD pre-coding is applied. Furthermore, the user equipment (UE) sets in the allocation sequences are eliminated with reinforcement learning. After the modification of a RR allocation sequence, no estimated throughput calculation for UE set selection is required. Numerical results obtained through computer simulation show that the maximum selection, one of the criteria for initial phase selection, outperforms the weighted PF scheduling in a restricted realm in terms of the computational complexity, fairness, and throughput.

High-accuracy wideband signal transmission is essential for 5G and Beyond wireless communication systems. Memory nonlinearity in transmitters is a serious issue for the goal, because it deteriorates the quality of signal and lowers the system performance. This paper studies a post-reception nonlinear compensation (PRC) schemes consisting of frequency domain equalizers (FDEs) and a blind nonlinear compensator (BNLC). A frequency-domain memory nonlinearity modeling approach is employed, and several PRC configurations with FDEs and BNLC are evaluated through computer simulations. It is concluded that the proposed PRC schemes can effectively compensate memory nonlinearity in wideband transmitters via frequency-selective propagation channel. By implementing the PRC in a base station, uplink performance will be enhanced without any additional cost and power consumption in user terminals.

Hardware oriented security and trust of semiconductor integrated circuit (IC) chips have been highly demanded. This paper outlines the requirements and recent developments in circuits and packaging systems of IC chips for security applications, with the particular emphasis on protections against physical implementation attacks. Power side channels are of undesired presence to crypto circuits once a crypto algorithm is implemented in Silicon, over power delivery networks (PDNs) on the frontside of a chip or even through the backside of a Si substrate, in the form of power voltage variation and electromagnetic wave emanation. Preventive measures have been exploited with circuit design and packaging technologies, and partly demonstrated with Si test vehicles.

This paper proposes a layer-wise tunable retraining method for edge FeFET Computation-in-Memory (CiM) to compensate the accuracy degradation of neural network (NN) by FeFET device errors. The proposed retraining can tune the number of layers to be retrained to reduce inference accuracy degradation by errors that occur after retraining. Weights of the original NN model, accurately trained in cloud data center, are written into edge FeFET CiM. The written weights are changed by FeFET device errors in the field. By partially retraining the written NN model, the proposed method combines the error-affected layers of NN model with the retrained layers. The inference accuracy is thus recovered. After retraining, the retrained layers are re-written to CiM and affected by device errors again. In the evaluation, at first, the recovery capability of NN model by partial retraining is analyzed. Then the inference accuracy after re-writing is evaluated. Recovery capability is evaluated with non-volatile memory (NVM) typical errors: normal distribution, uniform shift, and bit-inversion. For all types of errors, more than 50% of the degraded percentage of inference accuracy is recovered by retraining only the final fully-connected (FC) layer of Resnet-32. To simulate FeFET Local-Multiply and Global-accumulate (LM-GA) CiM, recovery capability is also evaluated with FeFET errors modeled based on FeFET measurements. Retraining only FC layer achieves recovery rate of up to 53%, 66%, and 72% for FeFET write variation, read-disturb, and data-retention, respectively. In addition, just adding two more retraining layers improves recovery rate by 20-30%. In order to tune the number of retraining layers, inference accuracy after re-writing is evaluated by simulating the errors that occur after retraining. When NVM typical errors are injected, it is optimal to retrain FC layer and 3-6 convolution layers of Resnet-32. The optimal number of layers can be increased or decreased depending on the balance between the size of errors before retraining and errors after retraining.

It is very important to design an embedded real-time system as a fault-tolerant system to ensure dependability. In particular, when a power failure occurs, restart processing after power restoration is required in a real-time system using a conventional processor. Even if power is restored quickly, the restart process takes a long time and causes deadline misses. In order to design a fault-tolerant real-time system, it is necessary to have a processor that can resume operation in a short time immediately after power is restored, even if a power failure occurs at any time. Since current embedded real-time systems are required to execute many tasks, high schedulability for high throughput is also important. This paper proposes a non-stop microprocessor architecture to achieve a fault-tolerant real-time system. The non-stop microprocessor is designed so as to resume normal operation even if a power failure occurs at any time, to achieve little performance degradation for high schedulability even if checkpoint creations and restorations are performed many times, to control flexibly non-volatile devices through software configuration, and to ensure data consistency no matter when a checkpoint restoration is performed. The evaluation shows that the non-stop microprocessor can restore a checkpoint within 5µsec and almost hide the overhead of checkpoint creations. The non-stop microprocessor with such capabilities will be an essential component of a fault-tolerant real-time system with high schedulability.

This paper presents a Ka-band high-efficiency power amplifier (PA) with a novel adaptively controlled gate capacitor circuit and a two-step adaptive bias circuit for 5th generation (5G) mobile terminal applications fabricated using a 45-nm silicon on insulator (SOI) CMOS process. The PA adopts a stacked FET structure to increase the output power because of the low breakdown voltage issue of scaled MOSFETs. The novel adaptive gate capacitor circuit properly controls the RF swing for each stacked FET to achieve high efficiency in the several-dB back-off region. Further, the novel two-step adaptive bias circuit effectively controls the gate voltage for each stacked FET for high linearity and high back-off efficiency. At a supply voltage of 4 V, the fabricated PA has exhibited a saturated output power of 20.0 dBm, a peak power added efficiency (PAE) of 42.7%, a 3dB back-off efficiency of 32.7%, a 6dB back-off efficiency of 22.7%, and a gain of 15.6 dB. The effective PA area was 0.82 mm by 0.74 mm.

This paper describes an in-depth analysis of crosstalk in a high-bandwidth 3D-stacked memory using a multi-hop inductive coupling interface and proposes two countermeasures. This work analyzes the crosstalk among seven stacked chips using a 3D electromagnetic (EM) simulator. The detailed analysis reveals two main crosstalk sources: concentric coils and adjacent coils. To suppress these crosstalks, this paper proposes two corresponding countermeasures: shorted coils and 8-shaped coils. The combination of these coils improves area efficiency by a factor of 4 in simulation. The proposed methods enable an area-efficient inductive coupling interface for high-bandwidth stacked memory.

Series-connection of resonant-tunneling diodes (RTDs) has been considered to be efficient in upgrading the output power when it is introduced to oscillator architecture. This work is for clarifying the same architecture also contributes to increasing oscillation frequency because the device parasitic capacitance is reduced M times for M series-connected RTD oscillator. Although this mechanism is expected to be universal, we restrict the discussion to the recently proposed multiphase oscillator utilizing an RTD oscillator lattice loop. After explaining the operation principle, we evaluate how the oscillation frequency depends on the number of series-connected RTDs through full-wave calculations. In addition, the essential dynamics were validated experimentally in breadboarded multiphase oscillators using Esaki diodes in place of RTDs.

This paper presents a hippocampal cognitive prosthesis chip designed for restoring the ability to form new long-term memories due to hippocampal system damage. The system-on-chip (SOC) consists of a 16-channel micro-power low-noise amplifier (LNA), high-pass filters, analog-digital converters (ADCs), a 16-channel spike-sorter, a generalized Laguerre-Volterra model multi-input, multi-output (GLVM-MIMO) hippocampal processor, an 8-channel neural stimulator and peripheral circuits. The proposed LNA achieved a voltage gain of 50dB, input-referred noise of 3.95µVrms, and noise efficiency factor (NEF) of 3.45 with the power consumption of 3.3µW. High-pass filters with a 300-Hz bandwidth are used to filter out the unwanted local field potential (LFP). 4 12-bit successive approximation register (SAR) ADCs with a signal-to-noise-and-distortion ratio (SNDR) of 63.37dB are designed for the digitization of the neural signals. A 16-channel spike-sorter has been integrated in the chip enabling a detection accuracy of 98.3% and a classification accuracy of 93.4% with power consumption of 19µW/ch. The MIMO hippocampal model processor predict output spatio-temporal patterns in CA1 according to the recorded input spatio-temporal patterns in CA3. The neural stimulator performs bipolar, symmetrical charge-balanced stimulation with a maximum current of 310µA, triggered by the processor output. The chip has been fabricated in 40nm standard CMOS technology, occupying a silicon area of 3mm2.

This study proposes a low-complexity permittivity estimation for ground penetrating radar applications based on a contrast source inversion (CSI) approach, assuming multilayered ground media. The homogeneity assumption for each background layer is used to address the ill-posed condition while maintaining accuracy for permittivity reconstruction, significantly reducing the number of unknowns. Using an appropriate initial guess for each layer, the post-CSI approach also provides the dielectric profile of a buried object. The finite difference time domain numerical tests show that the proposed approach significantly enhances reconstruction accuracy for buried objects compared with the traditional CSI approach.

High-performance deep neural network (DNN)-based systems are in high demand in edge environments. Due to its high computational complexity, it is challenging to deploy DNNs on edge devices with strict limitations on computational resources. In this paper, we derive a compact while highly-accurate DNN model, termed dsODENet, by combining recently-proposed parameter reduction techniques: Neural ODE (Ordinary Differential Equation) and DSC (Depthwise Separable Convolution). Neural ODE exploits a similarity between ResNet and ODE, and shares most of weight parameters among multiple layers, which greatly reduces the memory consumption. We apply dsODENet to a domain adaptation as a practical use case with image classification datasets. We also propose a resource-efficient FPGA-based design for dsODENet, where all the parameters and feature maps except for pre- and post-processing layers can be mapped onto on-chip memories. It is implemented on Xilinx ZCU104 board and evaluated in terms of domain adaptation accuracy, inference speed, FPGA resource utilization, and speedup rate compared to a software counterpart. The results demonstrate that dsODENet achieves comparable or slightly better domain adaptation accuracy compared to our baseline Neural ODE implementation, while the total parameter size without pre- and post-processing layers is reduced by 54.2% to 79.8%. Our FPGA implementation accelerates the inference speed by 23.8 times.

We developed a PYNQ cluster that consists of economical Zynq boards, called M-KUBOS, that are interconnected through low-cost high-performance GTH serial links. For the software environment, we employed the PYNQ open-source software platform. The PYNQ cluster is anticipated to be a multi-access edge computing (MEC) server for 5G mobile networks. We implemented the ResNet-50 inference accelerator on the PYNQ cluster for image recognition of MEC applications. By estimating the execution time of each ResNet-50 layer, layers of ResNet-50 were divided into multiple boards so that the execution time of each board would be as equal as possible for efficient pipeline processing. Owing to the PYNQ cluster in which FPGAs were directly connected by high-speed serial links, stream processing without network bottlenecks and pipeline processing between boards were readily realized. The implementation on 4 boards achieved 292 GOPS performance, 75.1 FPS throughput, and 7.81 GOPS/W power efficiency. It achieved 17 times faster speed and 130 times more power efficiency compared to the implementation on the CPU, and 5.8 times more power efficiency compared to the implementation on the GPU.

The issue of a low minority class identification rate caused by data imbalance in anomaly detection tasks is addressed by the proposal of a GAN-SR-based intrusion detection model for industrial control systems. First, to correct the imbalance of minority classes in the dataset, a generative adversarial network (GAN) processes the dataset to reconstruct new minority class training samples accordingly. Second, high-dimensional feature extraction is completed using stacked asymmetric depth self-encoder to address the issues of low reconstruction error and lengthy training times. After that, a random forest (RF) decision tree is built, and intrusion detection is carried out using the features that SNDAE retrieved. According to experimental validation on the UNSW-NB15, SWaT and Gas Pipeline datasets, the GAN-SR model outperforms SNDAE-SVM and SNDAE-KNN in terms of detection performance and stability.

In industry, automatic speech recognition has come to be a competitive feature for embedded products with poor hardware resources. In this work, we propose a tiny end-to-end speech recognition model that is lightweight and easily deployable on edge platforms. First, instead of sophisticated network structures, such as recurrent neural networks, transformers, etc., the model we propose mainly uses convolutional neural networks as its backbone. This ensures that our model is supported by most software development kits for embedded devices. Second, we adopt the basic unit of MobileNet-v3, which performs well in computer vision tasks, and integrate the features of the hidden layer at different scales, thus compressing the number of parameters of the model to less than 1 M and achieving an accuracy greater than that of some traditional models. Third, in order to further reduce the CPU computation, we directly extract acoustic representations from 1-dimensional speech waveforms and use a self-supervised learning approach to encourage the convergence of the model. Finally, to solve some problems where hardware resources are relatively weak, we use a prefix beam search decoder to dynamically extend the search path with an optimized pruning strategy and an additional initialism language model to capture the probability of between-words in advance and thus avoid premature pruning of correct words. In our experiments, according to a number of evaluation categories, our end-to-end model outperformed several tiny speech recognition models used for embedded devices in related work.

In CRYPTO 2019, Gohr first introduced the deep learning method to cryptanalysis for SPECK32/64. A differential-neural distinguisher was obtained using ResNet neural network. Zhang et al. used multiple parallel convolutional layers with different kernel sizes to capture information from multiple dimensions, thus improving the accuracy or obtaining a more round of distinguisher for SPECK32/64 and SIMON32/64. Inspired by Zhang's work, we apply the network structure to other ciphers. We not only improve the accuracy of the distinguisher, but also increase the number of rounds of the distinguisher, that is, distinguish more rounds of ciphertext and random number for DES, Chaskey and PRESENT.