We present a built-in self-reconfiguring system for a mesh-connected processor array where faulty processor elements are compensated for by spare processing elements located in one row and one column. It has advantages in that the number of spare processing elements is small and additional control circuits and networks for changing interconnections of processing elements is so simple that hardware overhead for reconfiguration is also small. First, to indicate the motivation to the proposed reconfiguration scheme, we briefly describe other schemes with the same number of spares as that of the proposed scheme where faulty processing elements are replaced using straight shifts toward spares, and compare their reconfiguration probabilities to each other. Then, we show that a variant of the proposed scheme has the highest probability. Next, we present a built-in self-reconfiguring system for the scheme and formally prove that it works correctly. It can automatically replace faulty processors by spare processors on detecting faults of processors.

As the capacity of a personal computer and workstation increases rapidly, many electromagnetic simulators solving antenna problems are widely used. In this paper, the IE3D, FIDELITY and HFSS electromagnetic simulators, which are commercial software products, are applied to the analysis of built-in antennas for handsets in the vicinity of the human body. The IE3D, FIDELITY and HFSS electromagnetic simulators are based on the methods of moment, FDTD (Finite Difference Time Domain) and FEM (Finite Element Method), respectively. Firstly, basic characteristics including the human body's effect of a popular built-in antenna for handset such as PIFA (Planar Inverted-F Antenna) are obtained by the IE3D, FIDELITY and HFSS electromagnetic simulators, and calculated results are compared with measured results. Secondly, on the basis of newly considered design concepts for a handset antenna, a folded loop antenna for handset, which we have proposed in order to reduce the influence of the human body, is taken as an example of a balance-fed antenna and is analyzed theoretically and experimentally including the influence of the human body. In a result, calculated results by these three kinds of electromagnetic simulators are in good agreement with measured results and it is confirmed that these simulators are very effective in analyzing the handset antenna in the vicinity of the human body.

This paper proposes a novel CMOS built-in current sensor (BICS) for on-line current testing. Proposed BICS detects abnormal current in circuit under test (CUT) and makes a Pass/Fail signal through comparison between the CUT current and the duplicated inverter current. This circuit consists of two current-to-voltage conversion transistors, a full swing generator, a voltage comparator, and an inverter block. It requires 16 transistors. Since this BICS does not require the extra clock, the added extra pin is only one output pin. Furthermore, the BICS does not require test mode selection. Therefore the BICS can be applied to on-line current testing. The validity and effectiveness are verified through the HSPICE simulation of circuits with defects. When the CUT is an 8 8 parallel multiplier, the area overhead of the BICS is about 4.34%.

This paper reviews antenna technologies for cellular phone terminal in Japan. In regard to the technologies two technical subjects are addressed: a diversity system and miniaturization of terminal size. These subjects provide motivation for studies on design methods for diversity antennas, development of built-in antennas, and control methods for surface current on terminal cavity. These studies are progressing.

This paper describes a novel IDDQ sensor circuit that is driven by only an abnormal IDDQ. The sensor circuit has relatively high sensitivity and can operate at a low supply voltage. Based on a very simple idea, it requires two additional power supplies. It can operate at either 5-V or 3.3-V VDD with the same design. Simulation results show that it can detect a 16-µA abnormal IDDQ at 3.3-V VDD. This sensor circuit causes a smaller voltage drop and smaller performance penalty in the circuit under test than other ones.

In this letter, a novel built-in self-test (BIST) structure based on operational transconductance amplifiers and grounded capacitors (OTA-Cs) for the fault diagnosis of analog circuits is proposed. The proposed analog BIST structure, namely ABIST, can be used to increase the number of test points, sampling and controlling of all test points with voltage data, and making less time for test signal observable. Experimental measurements have been made to verify that the proposed ABIST structure is effective.

The advantage of random testing is that test application can be performed at a low cost in the BIST scheme. However, not all circuits are random pattern testable due to the existence of random pattern resistant faults. In this paper, we present a method for improving the random pattern testability of logic circuits by partial circuit duplication approach. The basic idea is to detect random pattern resistant faults by using the difference between the duplicated part of a circuit and the original part. Experimental results on benchmark circuits show that high fault coverage can be achieved with a very small amount of hardware overhead.

Cellular automata (CA) implementations are expected as potential test-pattern generators (TPGs) for Built-In Self-Testing of VLSI circuits, in which highly random parallel patterns ought to be generated with simple hardware. Objective here is to design one-dimensional, binary, and linear CA implementations with cyclic boundary conditions that can operate on maximum length of period. To provide maximum period of operations, it is necessary to bring some irregularities into the configurations. It is also expected for TPGs to make maximum or sufficiently long period of operations to prevent re-initialization. Our approach is to generate transition matrices based on fast parallel implementations of LFSRs which have trinomials as characteristic polynomials and then to modify the diagonal components. Some notable properties of diagonal vectors were observed.

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ,m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e. g. , SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ,m)s or a parallel construction of the H original GLFSR(δ,m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

In the data path circuits of asynchronous systems, logical faults may first manifest as undetectable, transient wrong codewords, in spite of encoding the inputs and the outputs and proper organization which enables the faults to be propagated to the primary outputs in the form of non-codewords. Due to this, the conventional methods of concurrent error detection (CED) using the logic (voltage) monitoring is not effective. In this paper, we suggest a mixed-signal approach to achieve CED for a class of asynchronous circuits, known as self-timed circuits. First, we show that it is impossible to guarantee the CED using logic monitoring of the primary outputs in spite of proper encoding and organization of self-timed circuits. Then, we discuss different manifestations of single stuck-at faults occurring during normal operation in these circuits. Finally, we present the feasibility of achieving CED using a built-in current sensor (BICS) along with encoding techniques.

Built-in self-test (BIST) has been applied to test an analog to digital converter (ADC) and a digital to analog converter (DAC) embedded in a DSP-core ASIC. The eight performance characteristics of the ADC and the DAC designed in accordance with the ITU-T recommendations are measured using the BIST. Three of the eight characteristics - the attenuation/frequency distortion, the variation of gain with input level, and the signal-to-total distortion - have been evaluated and the measured results have shown good agreement with measured results by conventional tests. In the BIST operation, the DSP-core generates input stimulus and analyzes output response by control of the self-test program, The sizes of the self-test program and coefficient data are 822 words of the IROM and 384 words of the data ROM, respectively. This area overhead is less than 0.5% of total chip area. Test-time by the BIST is reduced to approximately 3.2 seconds, which is one-tenth that of conventional testing. The mixed-signal DSP-core ASIC is testable with only logic test equipment, and as a result, test-cost - that is test investment and test-time - is reduced compared with conventional test methods.

Superconductive LSIs with Josephson junctions have features such as low power dissipation and high switching speed. In this paper, we review our developed 4-Kbit RAM with vortex transitional memory cells as an illustration of superconductive LSIs with Josephson junctions. We have developed a fabrication process technology for the 4-Kbit RAM. In the 4-Kbit RAM, 380ps access time and 9.8 mW power dissipation have been experimentally obtained. And also, we have estimated a suitable moat structure to reduce the influence of trapped magnetic structure. The 4-Kbit RAM has been successfully operated with a bit yield of 99.8%. Furthermore, we discuss GHz testing which is one of the most significant issues concerning superconductive digital LSIs.

This paper proposes a distributed built-in self-test (BIST) technique and its test design platform for VLSIs. This BIST has lower hardware overhead pattern generators, compressors and controller. The platform cuts down on the number of complicated operations needed for the BIST insertion and evaluation, so the BIST implementation turn-around-time (TAT) is dramatically reduced. Experimental results for the 110 k-gate arithmetic execution blocks of an image-processing LSI show that using this BIST structure and platform enables the entire BIST implementation within five days. The implemented BIST has a 1% hardware overhead and 96% fault coverage. This platform will significantly reduce testing costs for time-to-market and mass-produced LSIs.

Transition coverage has been proposed as a measure of two-pattern test capabilities of TPG circuits for use in BIST. This paper investigates experimentally the relationships between transition coverages and actual stuck-open fault coverages in order to reveal what kind of circuits are appropriate for two-pattern testing. Fault simulation was performed using conventional (n-stage) LFSR, 2n-stage LFSR, and one-dimensional cellular automata (CAs) as TPG circuits and such sample circuits as balanced NAND tree and some ISCAS '85 benchmark circuits as CUTs. It was found that CAs which are designed so as to apply exhaustive transitions to any 3-dimensional subspaces can detect high rate of stuck-open faults. Influence of hazards of decreasing the fault coverage is also mentioned.

Current testing has been proposed as an alternative technique for testing fully CMOS digital LSIs. Current testing has higher fault coverage than conventional stuck-at fault (SAF) testing and is more economical because it detects a wide range of faults and requires fewer test vectors than does SAF testing. We have proposed a current testing that measures the integral of the power supply current (IDD) during one clock period including the switching current. Since this method cannot be affected by the switching current, it can be used to test an LSI operating at a relatively high clock freuqnecy. This paper presents an improved current testing method for CMOS digital and analog LSIs. The method uses two current values (i.e., an upper limit and a lower limit) and judges the circuit under test to be faulty if the measured IDD is outside these limits. The proposed current testing is evaluated here for some kinds of faults (e.g., the bridging fault and the breaking fault) in digital and mixed-signal LSIs, and its efficiency of the current testing using SPICE3.

Any minimum test set (MLTS) for locally exhaustive testing of multiple output combinational circuits (CUTs) has at least 2w test patterns, where w is the maximum number of inputs on which any output depends. In the previous researches, it is clarified that every CUT with up to four outputs has an MLTS with 2w elements. On the other hand, it can be easily shown that every CUT with more than five outputs does not have such an MLTS. It has not been however known whether every CUT with five outputs has such an MLTS or not. In this paper, it is clarified that every CUT with five outputs has such an MLTS. First, some terminologies are introduced as preliminaries. Second, features of 5(w1) dependence matrices of CUTs with five outputs and (w1) inputs are discussed. Third, an equivalence relation between dependence matrices of two CUTs is introduced. The relation means that if it holds and one of the CUTs has an MLTS with 2w elements, then the other CUT also has such an MLTS. Based on the features described above, a theorem is established that there exists a 5w dependence matrix which is equivalent to each of the above 5(w1) matrices. Finally, it is proved by the use of the theorem that every CUT with five outputs has an MLTS with 2 w elements.

A method to design one-dimensional cellular arrays to be used as TPG circuits of BIST is described. The interconnections between cells are not limited to adjacent ones but allowed to some neighbors. Completely regular structures that have full-transition coverages for every k-dimensional subspace of state variables are first shown. Then, almost regular arrays which can operate on maximum cycles are derived based on fast parallel implementations of LFSRs.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

The locally exhaustive testing of multiple output combinational circuits is the test which provides exhaustive test patterns for each set of inputs on which each output depends. First, this paper presents a sufficient condition under which a minimum test set (MLTS) for the locally exhaustive testing has 2w test patterns, where w is the maximum number of inputs on which any output depends. Next, we clarify that any CUT with up to four outputs satisfies the condition, independently of w and n, where n is the number of inputs of the CUT. Finally, we clarify that any CUT with five outputs also satisfies the condition for 1w2 or n2wn.

Signature analysis using a Multiple-Input LFSR as the output response compaction circuit is widely adopted in actual BIST schemes. While aliasing probabilities for random errors are usually very small, MI-LFSRs are tend to fail detecting diagonal errors. A spot error, which include the diagonal error as a particular case, is defined as multiple bit crrors adjacent in space and in time domain. Then, shuffling of interconnection between CUT output and MI-LFSR input is studied as a scheme to prevent aliasing for such errors. The condition for preventing aliasing due to a predetermined size of single spot error is shown. Block based shuffling and the shortened one are proposed to realize required distance properties. Effect of shuffling for multiple spot errors is examined by simulation showing that shuffling is effective also for a certain extend of multiple spot errors.