This paper presents a theoretical design of novel THz bandpass filters composed of M-PhC (metallic-photonic-crystal) point-defect-cavities (PDCs) with a centrally-loaded-rod. After a brief review of the properties of the recently-proposed M-PhC PDCs, two inline-type bandpass filters are synthesized in terms of the coupling matrix theory. The FDTD simulation results of the synthesized filters are in good agreement with the theoretical ones, which confirms the validity of the proposed filters' structures and the design scheme.

Properties of a class of M-PhC (metallic-photonic-crystal) point-defect-cavities (PDCs) with a centrally-loaded rod are theoretically and experimentally investigated. After the computation of the resonant frequencies and Q-factors of the resonant modes, the PDCs are fabricated and experimentally measured to validate the simulation results.

An transfer learning method, called Kernel Canonical Correlation Analysis plus (KCCA+), is proposed for heterogeneous Cross-company defect prediction. Combining the kernel method and transfer learning techniques, this method improves the performance of the predictor with more adaptive ability in nonlinearly separable scenarios. Experiments validate its effectiveness.

Class imbalance has drawn much attention of researchers in software defect prediction. In practice, the performance of defect prediction models may be affected by the class imbalance problem. In this paper, we present an approach to evaluating the performance stability of defect prediction models on imbalanced datasets. First, random sampling is applied to convert the original imbalanced dataset into a set of new datasets with different levels of imbalance ratio. Second, typical prediction models are selected to make predictions on these new constructed datasets, and Coefficient of Variation (C·V) is used to evaluate the performance stability of different models. Finally, an empirical study is designed to evaluate the performance stability of six prediction models, which are widely used in software defect prediction. The results show that the performance of C4.5 is unstable on imbalanced datasets, and the performance of Naive Bayes and Random Forest are more stable than other models.

In this letter, we propose a novel discriminative representation for patterned fabric defect inspection when only limited negative samples are available. Fisher criterion is introduced into the loss function of deep learning, which can guide the learning direction of deep networks and make the extracted features more discriminating. A deep neural network constructed from the encoder part of trained autoencoders is utilized to classify each pixel in the images into defective or defectless categories, using as context a patch centered on the pixel. Sequentially the confidence map is processed by median filtering and binary thresholding, and then the defect areas are located. Experimental results demonstrate that our method achieves state-of-the-art performance on the benchmark fabric images.

In this paper, a built-in test circuit for an electrical interconnect test method is proposed to detect an open defect occurring at an interconnect between an IC and a printed circuit board. The test method is based on measuring the supply current of an inverter gate in the test circuit. A time-varying signal is provided to an interconnect as a test signal by the built-in test circuit. In this paper, the test circuit is evaluated by SPICE simulation and by experiments with a prototyping IC. The experimental results reveal that a hard open defect is detectable by the test method in addition to a resistive open defect and a capacitive open one at a test speed of 400 kHz.

We propose an algorithm for the scattering analyses of gratings with various local defects based on the difference-field boundary-element method (DFBEM). In the algorithm, the defect in the grating is partitioned, and the DFBEM is sequentially applied for each defect section. We validate the proposed algorithm by demonstrating its flexibility for various defect topologies for a locally deformed grating.

With aggressive device scaling, timing failures have become more prevalent due to manufacturing defects and process variations. When timing failure occurs, it is important to take corrective actions immediately. Therefore, an efficient and fast diagnosis method is essential. In this paper, we propose a new diagnostic method using timing information. Our method approximately estimates all the segment delays of measured paths in a design, using inequality-constrained least squares methods. Then, the proposed method ranks the possible locations of delay defects based on the difference between estimated segment delays and the expected values of segment delays. The method works well for multiple delay defects as well as single delay defects. Experiment results show that our method yields good diagnostic resolution. With the proposed method, the average first hit rank (FHR), was within 7 for single delay defect and within 8 for multiple delay defects.

We evaluated software maintenance of an open source cloud platform system we developed using an agile software development method. We previously reported on a rapid service launch using the agile software development method in spite of large-scale development. For this study, we analyzed inquiries and the defect removal efficiency of our recently developed software throughout one-year operation. We found that the defect removal efficiency of our recently developed software was 98%. This indicates that we could achieve sufficient quality in spite of large-scale agile development. In term of maintenance process, we could answer all enquiries within three business days and could conduct version-upgrade fast. Thus, we conclude that software maintenance of agile software development is not ineffective.

With IC design entering the nanometer scale integration, the reliability of VLSI has declined due to small-delay defects, which are hard to detect by traditional delay fault testing. To detect small-delay defects, on-chip delay measurement, which measures the delay time of paths in the circuit under test (CUT), was proposed. However, our pre-simulation results show that when using on-chip delay measurement method to detect small-delay defects, test generation under the single-path sensitization is required. This constraint makes the fault coverage very low. To improve fault coverage, this paper introduces techniques which use segmented scan and test point insertion (TPI). Evaluation results indicate that we can get an acceptable fault coverage, by combining these techniques for launch off shift (LOS) testing under the single-path sensitization condition. Specifically, fault coverage is improved 27.02∼47.74% with 6.33∼12.35% of hardware overhead.

In recent VLSIs, small-delay defects, which are hard to detect by traditional delay fault testing, can bring about serious issues such as short lifetime. To detect small-delay defects, on-chip delay measurement which measures the delay time of paths in the circuit under test (CUT) was proposed. However, this approach incurs high test cost because it uses scan design, which brings about long test application time due to scan shift operation. Our solution is a test application time reduction method for testing using the on-chip path delay measurement. The testing with on-chip path delay measurement does not require capture operations, unlike the conventional delay testing. Specifically, FFs keep the transition pattern of the test pattern pair sensitizing a path under measurement (PUM) (denoted as p) even after the measurement of p. The proposed method uses this characteristic. The proposed method reduces scan shift time and test data volume using test pattern merging. Evaluation results on ISCAS89 benchmark circuits indicate that the proposed method reduces the test application time by 6.89∼62.67% and test data volume by 46.39∼74.86%.

Small delay defects can cause serious issues such as very short lifetime in the recent VLSI devices. Delay measurement is useful to detect small delay defects in manufacturing testing. This paper presents a design for delay measurement to detect small delay defects on global routing resources, such as double, hex and long lines, in a Xilinx Virtex 4 based FPGA. This paper also shows a measurement method using the proposed design. The proposed measurement method is based on an existing one for SoC using delay value measurement circuit (DVMC). The proposed measurement modifies the construction of configurable logic blocks (CLBs) and utilizes an on-chip DVMC newly added. The number of configurations required by the proposed measurement is 60, which is comparable to that required by stuck-at fault testing for global routing resources in FPGAs. The area overhead is low for general FPGAs, in which the area of routing resources is much larger than that of the other elements such as CLBs. The area of every modified CLB is 7% larger than an original CLB, and the area of the on-chip DVMC is 22% as large as that of an original CLB. For recent FPGAs, we can estimate that the area overhead is approximately 2% or less of the FPGAs.

Nano-scale VLSI design is facing the problems of increased test data volume. Small delay defects are becoming possible sources of test escapes, and high delay test quality and therefore a greater volume of test data are required. The increased test data volume requires more tester memory and test application time, and both result in test cost inflation. Test pattern ordering gives a practical solution to reduce test cost, where test patterns are ordered so that more defects can be detected as early as possible. In this paper, we propose a test pattern ordering method based on SDQL (Statistical Delay Quality Level), which is a measure of delay test quality considering small delay defects. Our proposed method orders test patterns so that SDQL shrinks fast, which means more delay defects can be detected as early as possible. The proposed method efficiently orders test patterns with minimal usage of time-consuming timing-aware fault simulation. Experimental results demonstrate that our method can obtain test pattern ordering within a reasonable time, and also suggest how to prepare test sets suitable as inputs of test pattern ordering.

An asymmetric classifier based on kernel partial least squares is proposed for software defect prediction. This method improves the prediction performance on imbalanced data sets. The experimental results validate its effectiveness.

Automatic thresholding is an important technique for rail defect detection, but traditional methods are not competent enough to fit the characteristics of this application. This paper proposes the Maximum Weighted Object Correlation (MWOC) thresholding method, fitting the features that rail images are unimodal and defect proportion is small. MWOC selects a threshold by optimizing the product of object correlation and the weight term that expresses the proportion of thresholded defects. Our experimental results demonstrate that MWOC achieves misclassification error of 0.85%, and outperforms the other well-established thresholding methods, including Otsu, maximum correlation thresholding, maximum entropy thresholding and valley-emphasis method, for the application of rail defect detection.

An active learning method, called Two-stage Active learning algorithm (TAL), is developed for software defect prediction. Combining the clustering and support vector machine techniques, this method improves the performance of the predictor with less labeling effort. Experiments validate its effectiveness.

Effects of conductive defects on unipolar resistive random access memory (RRAM) are investigated in order to reduce the operation current for high density and low power RRAM applications. It is clarified that forming voltage decreases with increasing charged conductive defects which are a source of conductive filament (CF) path and with decreasing cell thickness. Random circuit breaker (RCB) network simulation model which is a dynamic percolation simulation model is used to elucidate these effects. From this simulation results, the optimal cell thickness with sufficient conductive defect shows improved resistive switching characteristics such as low forming voltage, small set voltage distribution and low reset current. From the deep understanding of relationship between conductive defect in various cell thickness and other resistive switching parameters, RRAM with low forming voltage and reset current can be obtained and it will be one of the most promising next generation nonvolatile memories.

A kernel based asymmetric learning method is developed for software defect prediction. This method improves the performance of the predictor on class imbalanced data, since it is based on kernel principal component analysis. An experiment validates its effectiveness.

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

A new linearly tapered slot antenna (LTSA) with defected sides is proposed in this letter. Both sides are defected with half-dumbbell shape slots that may alter the surface current intensities on both sides. As the half-dumbbell size is increased, the 3-dB beamwidth of the proposed antenna is 4° and 6° lower in the E/H-plane, respectively, than these of the LTSA without defects. Accordingly, the measured gain is improved by up to 3.75 dB and the first side lobe level is lowered by about -10.8 dB and -5.8 dB in the E/H-planes, respectively.