LCD Automatic Vision Inspection (AVI) systems automatically detect defect features and measure their sizes via camera vision. AVI systems usually report different measurements on the same defect with some variations on position or rotation mainly because we get different images. This is caused by possible variations in the image acquisition process including optical factors, non-uniform illumination, random noise, and so on. For this reason, conventional area based defect measuring method has some problems in terms of robustness and consistency. In this paper, we propose a new defect size measuring method to overcome these problems. We utilize volume information which is completely ignored in the area based conventional defect measuring method. We choose a bell shape as a defect model for experiment. The results show that our proposed method dramatically improves robustness of defect size measurement. Given proper modeling, the proposed volume based measuring method can be applied to various types of defect for better robustness and consistency.

Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate.

Initial growth of GaP on Si substrates using metalorganic vapor phase epitaxy was studied. Si substrates were exposed to PH3 preflow for 15 s or 120 s at 830 after they were preheated at 925. Atomic force microscopy (AFM) revealed that the Si surface after preflow for 120 s was much rougher than that after preflow for 15 s. After 1.5 nm GaP deposition on the Si substrates at 830, GaP islands nucleated more uniformly on the Si substrate after preflow for 15 s than on the substrate after preflow for 120 s. After 3 nm GaP deposition, layer structures were observed on a fraction of Si surface after preflow for 15 s. Island-like structures remained on the Si surface after preflow for 120 s. After 6 nm GaP deposition, the continuity of GaP layers improved on both substrates. However, AFM shows pits that penetrated a Si substrate with preflow for 120 s. Transmission electron microscopy of a GaP layer on the Si substrate after preflow for 120 s revealed that V-shaped pits penetrated the Si substrate. The preflow for a long time roughened the Si surface, which facilitated the pit formation during GaP growth in addition to degrading the surface morphology of GaP at the initial growth stage. Even after 50 nm GaP deposition, pits with a density on the order of 107 cm-2 remained in the sample. A 50-nm-thick flat GaP surface without pits was achieved for the sample with PH3 preflow for 15 s. The PH3 short preflow is necessary to produce a flat GaP surface on a Si substrate.

We have proposed and successfully demonstrated a two step method for localizing defects on an LSI chip. The first step is the same as a conventional laser-SQUID (L-SQUID) imaging where a SQUID and a laser beam are fixed during LSI chip scanning. The second step is a new L-SQUID imaging where a laser beam is stayed at the point, located in the first step results, during SQUID scanning. In the second step, a SQUID size (Aeff) and the distance between the SQUID and the LSI chip (ΔZ) are key factors limiting spatial resolution. In order to improve the spatial resolution, we have developed a micro-SQUID and the vacuum chamber housing both the micro-SQUID and the LSI chip. The Aeff of the micro-SQUID is a thousand of that of a conventional SQUID. The minimum value of ΔZ was successfully reduced to 25 µm by setting both the micro-SQUID and an LSI chip in the same vacuum chamber. The spatial resolution in the second step was shown to be 53 µm. Demonstration of actual complicated defects localization was succeeded, and this result suggests that the two step localization method is useful for LSI failure analysis.

To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.

Physical defects that are not covered by stuck-at fault or bridging fault model are increasing in LSI circuits designed and manufactured in modern Deep Sub-Micron (DSM) technologies. Therefore, it is necessary to target non-stuck-at and non-bridging faults. A stuck-open is one such fault model that captures transistor level defects. This paper presents two methods for maximizing stuck-open fault coverage using stuck-at test vectors. In this paper we assume that a test set to detect stuck-at faults is given and we consider two formulations for maximizing stuck-open coverage using the given test set as follows. The first problem is to form a test sequence by using each test vector multiple times, if needed, as long as the stuck-open coverage is increased. In this case the target is to make the resultant test sequence as short as possible under the constraint that the maximum stuck-open coverage is achieved using the given test set. The second problem is to form a test sequence by using each test vector exactly once only. Thus in this case the length of the test sequence is maintained as the number of given test vectors. In both formulations the stuck-at fault coverage does not change. The effectiveness of the proposed methods is established by experimental results for benchmark circuits.

It is very important to guarantee the quality of the industrial products by means of visual inspection. In order to reduce the soldering defect with terminal deformation and terminal burr in the manufacturing process, this paper proposes a 3D visual inspection system based on a stereo vision with single camera. It is technically noted that the base line of this single camera stereo was precisely calibrated by the image processing procedure. Also to extract the measuring point coordinates for computing disparity; the error is reduced with original algorithm. Comparing its performance with that of human inspection using industrial microscope, the proposed 3D inspection could be an alternative in precision and in processing cost. Since the practical specification in 3D precision is less than 1 pixel and the experimental performance was around the same, it was demonstrated by the proposed system that the soldering defect with terminal deformation and terminal burr in inspection, especially in 3D inspection, was decreased. In order to realize the inline inspection, this paper will suggest how the human inspection of the products could be modeled and be implemented by the computer system especially in manufacturing process.

In this paper a novel method for the purpose of random texture defect detection using a collection of 1-D HMMs is presented. The sound textural content of a sample of training texture images is first encoded by a compressed LBP histogram and then the local patterns of the input training textures are learned, in a multiscale framework, through a series of HMMs according to the LBP codes which belong to each bin of this compressed LBP histogram. The hidden states of these HMMs at different scales are used as a texture descriptor that can model the normal behavior of the local texture units inside the training images. The optimal number of these HMMs (models) is determined in an unsupervised manner as a model selection problem. Finally, at the testing stage, the local patterns of the input test image are first predicted by the trained HMMs and a prediction error is calculated for each pixel position in order to obtain a defect map at each scale. The detection results are then merged by an inter-scale post fusion method for novelty detection. The proposed method is tested with a database of grayscale ceramic tile images.

An unequal Wilkinson power divider with adjustable power dividing ratio is proposed. The proposed power divider consists of rectangular defected ground structure (DGS), isolated island in DGS, and varactor diodes. The impedance of the microstrip line greatly increases due to the DGS, and varies because of the varying capacitance of diodes. The measured unequal dividing ratios vary from 1.97-13.4 and 2.25-10.6 when 2- and 4-diodes are adopted.

If a test set for more complex faults than stuck-at faults is generated, higher defect coverage would be obtained. Such a test set, however, would have a large number of test vectors, and hence the test costs would go up. In this paper we propose a method to detect bridge defects with a test set initially generated for stuck-at faults in a full scan sequential circuit. The proposed method doesn't add new test vectors to the test set but modifies test vectors. Therefore there are no negative impacts on test data volume and test application time. The initial fault coverage for stuck-at faults of the test set is guaranteed with modified test vectors. In this paper we focus on detecting as many as possible non-feedback AND-type, OR-type and 4-way bridging faults, respectively. Experimental results show that the proposed method increases the defect coverage.

A method for detecting interconnect open faults of CMOS combinational circuits by applying a ramp voltage to the power supply terminal is proposed. The method can assign a known logic value to a fault location automatically by applying a ramp voltage and as a result, it requires only one test vector to detect a fault as a delay fault or an erroneous logic value at primary outputs. In this paper, we show fault detectability and effectiveness of the proposed method by simulation-based and theoretical analysis. We also expose that the method can be applicable to every fault location in a circuit and open faults with any value. Finally, we show ATPG results that are suitable to the proposed method.

A novel dual mode bandpass filter (BPF) with improved spurious response is presented in this letter. To obtain low insertion loss, the coupling structure using the dual mode resonator and the feeding scheme using coplanar-waveguide (CPW) are constructed on the two sides of a dielectric substrate. A defected ground structure (DGS) is designed on the ground plane of the CPW to achieve the goal of spurious suppression of the filter. The filter has been investigated numerically and experimentally. Measured results show a good agreement with the simulated analysis.

This paper deals with the scattering of a TM plane wave from a periodic grating with single defect, of which position is known. The surface is perfectly conductive and made up with a periodic array of rectangular grooves and a defect where a groove is not formed. The scattered wave above grooves is written as a variation from the diffracted wave for the perfectly periodic case. Then, an integral equation for the scattering amplitude is obtained, which is solved numerically by use of truncation and the iteration method. The differential scattering cross section and the optical theorem are calculated in terms of the scattering amplitude and are illustrated in figures. It is found that incoherent Wood's anomaly appears at critical angles of scattering. The physical mechanisms of Wood's anomaly and incoherent Wood's anomaly are discussed in relation to the guided surface wave excited by the incident plane wave. It is concluded that incoherent Wood's anomaly is caused by the diffraction of the guided surface wave.

A method to detect open node defects that cannot be detected by the conventional IDDQ test method has previously been proposed employing a sinusoidal wave superposed on the DC supply voltage. The present paper proposes a strategy to improve the detectability of the test method by means of frequency analysis of the supply current. In this strategy, defects are detected by determining whether secondary harmonics of the sinusoidal wave exist in the supply current. The effectiveness of the method is confirmed by experiments on two CMOS NAND gate packages (SSIs).

This paper deals with the scattering of TE plane wave from a periodic grating with single defect, of which position is known. The surface is perfectly conductive and made up with a periodic array of rectangular grooves and a defect where a groove is not formed. By use of the modal expansion method, the field inside grooves is expressed as a sum of guided modes with unknown amplitudes. The mode amplitudes are regarded as a sum of the base component and the perturbed component due to the defect, where the base component is the solution in case of the perfectly periodic grating. An equation for the base component is obtained in the first step. By use of the base component, a new equation for the perturbed component is derived in the second step. A new representation of the optical theorem, relating the total scattering cross section with the reduction of the scattering amplitude is obtained. Also, a single scattering approximation is proposed to express the scattered field. By use of truncation, we numerically obtain the base component and the perturbed component, in terms of which the total scattering cross section and the differential scattering cross section are calculated and illustrated in figures.

We report on a channel drop filter with a mode gap in the propagating mode of a photonic crystal slab that was fabricated on silicon on an insulator wafer. The results, simulated with the 3-dimensional finite-difference time-domain and plane-wave methods, demonstrated that an index-guiding mode for the line defect waveguide of a photonic crystal slab has a band gap at wave vector k = 0.5 for a mainly TM-like light-wave. The mode gap works as a distributed Bragg grating reflector that propagates the light-wave through the line defect waveguide, and can be used as an optical filter. The filter bandwidth was varied from 1-8 nm with an r/a (r: hole radius, a: lattice constant) variation around the wavelength range of 1550-1600 nm. We fabricated a Bragg reflector with a photonic crystal line-defect waveguide and Si-channel waveguides and by measuring the transmittance spectrum found that the Bragg reflector caused abrupt dips in transmittance. These experimental results are consistent with the results of the theoretical analysis described above. Utilizing the Bragg reflector, we fabricated channel dropping filters with photonic crystal slabs connected between channel waveguides and demonstrated their transmittance characteristics. They were highly drop efficient, with a flat-top drop-out spectrum at a wavelength of 1.56 µm and a drop bandwidth of 5.8 nm. Results showed that an optical add-drop multiplexer with a 2-D photonic crystal will be available for application in WDM devices for photonic networks and for LSIs in the near future.

We determine the annealing dynamics of AsGa antisite defects in As ion-implanted GaAs. An Arrhenius plot of the carrier decay rate or the defect density vs. the annealing temperature in the high temperature regime gives an energy EPA, which is different from true activation energy. The annealing time dependence of EPA obtained by the two diffusion models (self diffusion of AsGa antisite defects and VGa vacancy assisted diffusion of AsGa antisite defects) are compared with EPA's obtained from already published works. The results prove that the diffusion of AsGa antisite defects is assisted by the VGa vacancy defects that exist in a high density.

In [1] the impact of BIST on the chip defect level after test has been addressed. It was assumed in [1] that no measures are taken to ensure that the BIST circuitry is fault-free before launching the functional test. In this paper we assume that a BIST pretest is first conducted in order to get rid of all chips that fail it. Only chips whose BIST circuitry has passed the pretest are kept, while the rest are discarded. The BIST pretest, however, is assumed to have only a limited coverage against its own faults. This paper studies the product quality improvements as induced by the BIST pretest, and provides some insight as to when it may be worthwhile to perform it.

Large liquid crystal display (LCD) panels have several cell-gap problems. For example, gravity defects are observed as thicker cell-gap areas at the bottom of an LCD panel at a high temperature, and cold-bubble defects are observed as bubbles in an LCD panel at a low temperature. We have developed a gap simulation to investigate these problems. The calculation was carried out for both column and ball spacers. It was shown that gap defects can be substantially reduced using ball spacers.

To increase the yield of data processing circuits such as adders and logic operation circuits, the bit-slice reconfiguration design has been proposed as an efficient redundant technology for defect-tolerance. Wallace multipliers are a well-known class of high-speed parallel multipliers. Unfortunately, the bit-slice reconfiguration design is not applicable to Wallace multipliers because Wallace multipliers do not have regular bit-slice structure. Therefore, redundant designs for Wallace multipliers have been regarded impossible. This paper proposes a redundant design for Wallace multipliers. In order to design redundant Wallace multipliers, first, 2n heterogeneous slices are considered in a non-redundant nn Wallace multiplier. The proposed redundant Wallace multipliers contain reconfigurable slices which can play the role of both i-th and (i+1)-th slices. Since the i-th slice has a similar structure to the (i+1)-th slice, the reconfigurable slice is not much larger than the i-th slice. This paper also shows a repair procedure for the proposed design. This paper evaluates the proposed design from the viewpoint of the yield, area, effective yield and delay time. For example, the yield of a 3232 Wallace multiplier increases from 0.30 to 0.41 by applying the proposed design while the area increases by a factor of 1.21.