The reduction of the drain current for InGaAs/AlGaAs pseudomorphic high electron mobility transistors (PHEMTs) has been observed due to the RIE-damage induced under the gate region. However, it has been found that the drain current can be recovered after the gate-drain reverse current stress even at room temperature. The recovery rate of the drain current strongly depends on the gate-drain reverse current density. The activation energy of the recovery rate has been confirmed to decrease from 0.531 eV to 0.119 eV under the gate-drain reverse current stress. This phenomenon can be understood as a recombination enhanced defect reaction of holes generated by the avalanche breakdown. The non-radiative recombination of holes at the defect level is believed to enhance the recovery of the RIE-damage.

This paper proposes a precise method of realizing simultaneous measurement of microscopic defects and the macroscopic three-dimensional shapes of planar objects having specular reflection surfaces. The direction vector field of surface tilt is evaluated directly by the introduction of a moving slit-light technique based on computer graphic animation. A reflected image created by the moving slit-light is captured by a video camera, and the image sequence of the slit-light deformation is analyzed. The obtained direction vector field of the surface tilt recovers the surface shape by means of integration. Two sample objects, a concave mirror and a plane plastic injection molding, are tested to measure the performance of the proposed method. Surface anomalies such as surface dent and warpage are detected quantitatively at a high resolution (about 0.2 [µm]) and a high accuracy (about 95%) in a wide area (about 15 [cm]) of the test object.

This paper reports the implementation in three dimensions (3D) of diffusion models for low dose implanted dopants in silicon and the various numerical issues associated with it. In order to allow the end-users to choose between high accuracy or small calculation time, a conventional and 5-species diffusion models have been implemented in the 3D module DIFOX-3D belonging to the PROMPT plateform. By comparison with one and two-dimensional (1D and 2D) simulations performed with IMPACT-4, where calibrated models exist, the validity of this 3D models have been checked. Finally, the results obtained for a 3-dimensional simulation of a rapid thermal annealing step involved in the manufacturing of a MOS transistor are presented what show the capability of this module to handle the optimization of real devices.

This paper reports a Monte Carlo calculation of the bimolecular reaction of arsenic precipitation. As the accuracy of the numerical solution for the coupled rate equations strongly depends on the size of grid spacing, it is necessary to choose adequate number of rate equations in order to understand the behavior of the extended defects. Therefore, we developed a general kinetic Monte Carlo model for the extended defects, which explicitly takes the time evolution of the size density of the extended defects into account. The Monte Carlo calculation exhibits a quantitative agreement with the experimental data for deactivation, and successfully reproduces the rapid deactivation at the beginning phase followed by slow deactivation in the subsequent steps.

This paper deals with the fundamental problem of automatic assessment of appearance of seam puckers on suits, and suggests possibilities for practical usage. Presently, evaluations are done by inspectors who compare standard photographs of suits to test samples. In order to avoid human errors, however, a method of automatic evaluation is desired. We process the problem as pattern recognition. As a feature we use fractal dimensions. The fractal dimensions obtained from standard photographs are used as template patterns. To make it easier to calculate fractal dimensions, we plot a curve representing the appearance of seam puckers, from which fractal dimensions of the curve can be calculated. The seam puckers in gray-scale images are confused with the material's texture, so the seam puckers must be enhanced for a precise evaluation. By using the concept of variance, we select images with seam puckers and enhance only the images with seam puckers. This is the novel aspect of this work. Twenty suits are used for the evaluation experiment and we obtain a result almost the same to the evaluation gained by inspection. That is, the evaluation of 11 samples is the same as that gained by inspection, the results of 8 samples differ by 1 grade, and the evaluation of 1 sample has a 2-grade difference. The results are also compared to the evaluation of the system using the Daubechies wavelet feature. The result of comparison shows that the present method gives a better evaluation than the system using the Daubechies wavelet.

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and Horse-allocation) are introduced and compared.

Anomalous leakage current which flows between source and drain in thin film SOI MOSFET's is investigated. It is confirmed that the leakage current is caused by enhanced diffusion of the source/drain dopants along the LOCOS-induced crystal defects. Stress analysis by 2D simulation reveals that thinning a buried-oxide effectively suppresses deformation of an SOI film associated with over-oxidation during LOCOS. It is experimentally confirmed that using a SIMOX substrate which has a thinner buried-oxide causes no noticeable deformation of the SOI film nor anomalous leakage current.

In this paper we present a rigorous vector 3D lithography simulator METROPOLE-3D which is designed to run moderately fast on conventional engineering workstations. METROPOLE-3D solves Maxwell's equations rigorously in three dimensions to model how the non-vertically incident light is scattered and transmitted in non-planar structures. METROPOLE-3D consists of several simulation modules: photomask simulator, exposure simulator, post-exposure baking module and 3D development module. This simulator has been applied to a wide range of pressing engineering problems encountered in state-of-the-art VLSI fabrication processes, such as layout printability/manufacturability analysis including reflective notching problems and optimization of an anti-reflective coating (ARC) layer. Finally, a 3D contamination to defect transformation study was successfully performed using our rigorous simulator.

This paper describes a defect detection method which automatically extracts defect information from complicated background LSI patterns. Based on a scanning electron microscope (SEM) image, the defects on the wafer are characterized in terms of their locations, sizes and the shape of defects. For this purpose, two image processing techniques, the Hough transform and wavelet transform, have been employed. Especially, the Hough Transform for circles is applied to non-circular defects for estimating the shapes of defects. By experiments, it has been demonstrated that the system is very effective in defect identification and will be used as an integral part in future automatic defect pattern classification systems.

Recent years have seen great advances in our understanding and modeling of the coupled diffusion of dopants and defects in silicon during integrated circuit fabrication processes. However, the ever-progressing shrinkage of device dimensions and tolerances leads to new problems and a need for even better models. In this review, we address some of the advances in the understanding of defect-mediated diffusion, focusing on the equations and parameters appropriate for modeling of dopant diffusion in submicron structures.

This paper reports the evaluation results of the channel boron distribution in the deep sub-0.1 [µm] n-MOSFETs for the first time. It has been found that the boron depletion effect becomes dominant and the reverse short channel effect becomes less significant in the deep sub-0.1 [µm] n-MOSFETs. It has been also found that the sheet charge distribution responsible for the reverse short channel effect is localized within a distance of 100 [nm] from the source/drain-extension junction.

An automatic defect classification system (ADC) for use in visual inspection of semiconductor wafers is introduced. The methods of extracting the defect features based on the human experts' knowledge, with their correlations with the defect classes are elucidated. As for the classifier, Hyperellipsoid Clustering Network (HCN) which is a layered network model employing second order discrimination borders in the feature space, is introduced. In the experiments using a collection of defect images, the HCNs are compared with the conventional multilayer perceptron networks. There, it is shown that the HCN's adaptive hyperellipsoidal discrimination borders are more suited for the problem. Also, the cluster encapsulation by the hyperellipsoidal border enables to determine rejection classes, which is also desirable when the system will be in actual use. The HCN with rejection achieves, an overall classification rate of 75% with an error rate of 18%, which can be considered equivalent to those of the human experts.

We have improved the optical beam induced resistance change (OBIRCH) system so as to detect (1) a current path as small as 10-50 µA from the rear side of a chip, (2) current paths in silicide lines as narrow as 0. 2 µm, (3) high-resistance Ti-depleted polysilicon regions in 0. 2 µm wide silicide lines, and (4) high-resistance amorphous thin layers as thin as a few nanometers at the bottoms of vias. All detections were possible even in observation areas as wide as 5 mm 5 mm. The physical causes of these detections were characterized by focused ion beam and transmission electron microscopy.

We have specified typical fabrication defects of the current injection logic gates with four Josephson junctions (4JL gates), and then investigated the voltage and current behavior of defective gates by SPICE simulation to evaluate the defect coverage achieved by logic testing and current testing. The simulation results show that current testing may possibly achieve a high defect coverage while logic testing cannot detect almost half defects.

Using transmission electron microscopy (TEM), we studied structural defects in a Sr0. 7Bi2. 3Ta2O9 (SBT) thin film to be used for ferroelectric memory devices. We examined the effects of the substrate, crystal continuity, and dislocations in crystals as major causes of defects. For this study, we used an SBT thin film grown from an alkoxide solution. Since crystal growth was hardly influenced by the substrate, the substrate had little influence on the occurrence of defects resulted in misfit of lattice constant. Regions of partially low crystal continuity were observed in the SBT thin film. In these regions, the orientation was still uniform, but the continuity of the crystal grain was low because of the defects. In addition, variation in contrast was observed in the crystals, however, no obvious variation in chemical composition was found in this region of varying contrast. Therefore, the contrast variation is considered to be attributed to the dislocation. Such a dislocation was found to be occurred in the direction of the (2010) plane in many instances. The defects in the SBT film were also confirmed by the TEM observation.

The authors previously proposed a reconfigurable architecture called the "XL-scheme" in order to cope with processor element (PE) faults as well as link faults. However, they described an algorithm for compensating only for link faults. They determined the potential ability to tolerate faults of the XL-scheme for simultaneous faults of links and PEs, and left a reconstruction algorithm for simultaneous PE and link faults to be studied in the future. This paper briefly explains the XL-scheme and gives a reconstruction algorithm for simultaneous PE and link faults. The algorithm first replaces faulty PEs with healthy ones and then replaces faulty links with healthy ones. We then compute the reliabilities of the mesh-arrays with simultaneous PE and link faults by simulation. We compare the reliability of the XL-scheme with that of the one-and-half track switch model. It is seen that the former is much larger than the latter. Furthermore, we show the result for processing time.

The defects in the cold rolled strips have textural characteristics, which are nonuniform due to its irregularities and deformities in geometrical appearance. In order to handle the textural characteristics of images with defects, this paper proposes a surface inspection method based on textural feature extraction using the wavelet transform. The wavelet transform is employed to extract local features from textural images with defects both in the frequency and in the spatial domain. To extract features effectively, an adaptive wavelet packet scheme is developed, in which the optimum number of features are produced automatically through subband coding gain. The energies for all subbands of the optimal quadtree of the adaptive wavelet packet algorithm and four entropy features in the level one LL subband, which correspond to the local features in the spatial domain, are extracted. A neural network is used to classify the defects of these features. Experiments with real image data show good training and generalization performances of the proposed method.

This paper proposes a new duplication redundancy technology, 2 Transistors for 1.5 Gates, that is capable of automatic defect tolerance, so making large, high-resolution, color TFT-LCD panel fabrication both easy and economical. This redundancy technology with automatic defect tolerant capability has a low hardware overhead and is very capable of compensating for open circuit defects in a large active-matrix panel. This technology was confirmed by fabricating a 9.5-inch color TFT-LCD panel with 640480 pixels(960960 dots). This panel showed excellent display performance and produced pictures without defects. The yield improvement effect of this technology was also confirmed by calculation based on the Boltzmann statistics model. Consequently, this technology is clearly seen to have a yield improvement effect equal to defect density reduction of about one order, compared to non redundancy. This technology drastically reduces dot and line defects, enabling fabrication of large, high-resolution, color TFT-LCD panels at a relatively low cost.

In order to simulate the mechanism of particle growth by film deposition, imaginary-particle formation method has been newly developed. By using this formation method, the particle size, the particle height and the position of particle on a wafer could be controlled very easily. In this study, the imaginary-particles of various size larger than 0.15 micron and various height were formed on a wafer. By using these imaginary-particles, the effects of a deposition method, a film thickness, a particle size and a particle height upon the particle growth were investigated. As deposition methods, low pressure CVD method, plasma CVD method and sputtering method were compared. As a result, in all deposition method, it's clear that the particle growth doesn't depend on the initial size, and is proportional to the film thickness. Their particle growth rates are characterized by the deposition method, and their values are 1.9, 1.1 and 0.64 in low pressure CVD, plasma CVD and sputtering method, respectively. These values can be explained by the step coverage decided by the deposition method. Furthermore, the particle growth on imaginary-particle was compared with that on the real-particle. It is clear that the growth mechanism of the real-particle is closely similar to that of imaginary-particle, and the study by use of the imaginary-particle is very effective to make clear the mechanism of particle growth. Therefore, the particle size which should be controlled before deposition process is necessary to be decided by counting the particle growth shown in this paper.

A new observation technique for process-induced micro-defects in ULSI using a combination of anodic oxidation and chemical removal of the oxide has been developed. Enhanced oxidation has occurred at the defect region due to the stress field and then craterlike delineation has been formed after oxide removal. AFM and SEM observation of the micro-defects induced by ion implantation and applications using this tech-nique to the failure analysis of MOS device fabrication are presented.