We have fabricated and investigated InGaAs Esaki tunnel diodes, grown on GaAs or InP substrates, of varied defect densities. The tunnel diodes exhibit the same I-V characteristics in spite of the variation of defect density. Under the simple thermal annealing and forward current stress tests, the change in the valley current was not observed, indicating that defects were not increased. On the other hand, the reduction in the peak current due to the carbon diffusion was observed under both tests. The diffusion was enhanced by the stress current owing to the energy dissipation associated with the nonradiative electron-hole recombination. From the reduction rates of the peak current, we obtained the thermal and current-enhanced carbon diffusion constants in InGaAs, which are independent of defect density. Although thermal diffusion of carbon in InGaAs is comparable with that in GaAs, the current-induced enhancement of diffusion in InGaAs is extremely weaker than that in GaAs. The difference between activation energy of thermal and current-enhanced diffusion is 0.8 eV, which is independent of stress current density and close to InGaAs bandgap energy. This indicates that the current-enhanced diffusion is dominated by the energy dissipation associated with nonradiative band-to-band recombination. This enhancement mechanism well explains that the current-induced enhancement is independent of defect density and extremely weak. We also have found that the current-enhanced diffusion constant is approximately proportional to the square of current density, suggesting that the recombination in the depletion layer dominates the current-enhanced diffusion.

In this paper, a 2-D iteratively reweighted least squares lattice algorithm, which is robust to the outliers, is introduced and is applied to defect detection problem in textured images. First, the philosophy of using different optimization functions that results in weighted least squares solution in the theory of 1-D robust regression is extended to 2-D. Then a new algorithm is derived which combines 2-D robust regression concepts with the 2-D recursive least squares lattice algorithm. With this approach, whatever the probability distribution of the prediction error may be, small weights are assigned to the outliers so that the least squares algorithm will be less sensitive to the outliers. Implementation of the proposed iteratively reweighted least squares lattice algorithm to the problem of defect detection in textured images is then considered. The performance evaluation, in terms of defect detection rate, demonstrates the importance of the proposed algorithm in reducing the effect of the outliers that generally correspond to false alarms in classification of textures as defective or nondefective.

In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.

This investigation proposed a novel dual-mode circular patch bandpass filter (BPF) with enhanced stopband performance. The novelty of the proposed structure is to use a pair of square etched areas acting as a perturbation element on the circular patch resonator such that two split modes are coupled and the filter structure can be reduced. The coupling coefficients of two split modes are obtained. To improve the stopband performance, a pairs of H-shaped defected ground structure (DGS) cells are used below the input/output port to suppress the spurious response of the proposed BPF. The equivalent circuit of the DGS cell is discussed and the relations between bandstop characteristic and the suitable DGS dimensions are also investigated. The proposed BPF is demonstrated with a central frequency fo = 2.2 GHz, a 3-dB fractional bandwidth of 8% and a wider stopband of -35 dB from 2.5 to 6 GHz. Measured results of experimental filter have good agreement with the theoretical simulated results.

This paper proposes a cell layout synthesis technique to minimize the sensitivity to wiring faults due to spot defects. We modeled the sensitivity to faults on intra-cell routings with consideration to the spot defects size distribution and the end effect of critical areas. The effect of the sensitivity reduction on the yield is also discussed. By using the model as a cost function, we comprehensively generate the minimum width layout of CMOS logic cells and select the optimal layouts. Experimental results show that our technique reduces about 15% of the fault sensitivities compared with the wire-length-minimum layouts for benchmark CMOS logic circuits which have up to 14 transistors.

Built-in self-test (BIST) hardware is included today in many chips. This hardware is used to test the chip's functional circuits. Since this BIST hardware is manufactured using the same technology as the functional circuits themselves, it is possible for it to be faulty. It is important, therefore, to assess the impact of this unreliable BIST on the product defect level after test. Williams and Brown's formula, relating the product defect level as a function of the manufacturing yield and fault coverage, is re-examined in this paper. In particular, special attention is given to the influence of an unreliable BIST on this relationship. We show that when the BIST hardware is used to screen the functional product, an unreliable BIST circuitry tends, in many cases, to reduce the effective fault coverage and increase the corresponding product defect level. The BIST unreliability impact is assessed for both early life phase, and product maturity phase.

Carbon fiber composites are increasingly used as structural materials because of their unique and advantageous characteristics. Carbon fiber reinforced carbon matrix composite (C/C) has the characteristics of high fatigue resistance, fracture toughness and heat resistance up to 3000 K, and is an important component of refractory tiles and nozzles in space shuttles. Useful nondestructive testing methods for C/C are now required. We have developed a SQUID-NDT system based on a non-magnetic coaxial pulse tube cryocooler (PTC), a HTS-SQUID gradiometer and a field generator with ferrite cores that induces high currents in specimens with low electric conductivity. The cryostat with the PTC is compact, at 50 mm in diameter and 400 mm in height. It weighs a total of 4 kg. The system noise is 80 µ0/Hz1/2 corresponding to 1.3 nT/m/Hz1/2 at 100 Hz. We used the system to investigate the usefulness of the SQUID-NDT in detecting flaws in C/C composites. Hidden cracks in C/C multi-layered specimens were detected up to depth of 15 mm. Hidden cracks in C/C-Al stacked sample was also clearly detected. In addition, we magnetically detected the mechanical breaking process of a C/C specimen under tensile load using the current injection method. For this study, a technique for visualizing current detouring defects was developed for detection of deteriorating areas in the specimen. The deteriorating area, identified from the current map, expands during breaking process and agrees with the results obtained by the microscopic observation of the breaking process. The interrupted current Iint, estimated by summing the detour current, clearly changed depending on the stage of the breaking process, suggesting that Iint may be applicable as good index for distinguishing each stage in the breaking process. It is concluded that a SQUID-NDT is applicable to C/C composites and advanced complex materials with low electric conductivity in addition to metallic materials.

In this Letter, a dumbbell-shaped patch loaded slotline(PLS) is proposed. Like the conventional defected ground structure(DGS) for a microstrip line, we show that the proposed PLS can provide a wide bandstop characteristic in some frequency bands with only one or small number of unit cells. Also, the equivalent circuit model for a unit section is derived from the analysis of the field distributions in the structure and its circuit parameters are determined by means of full wave numerical simulations. This equivalent circuit is shown to be dual to that of the typical DGS in a microstrip line. A broadband microstrip to slotline transition is incorporated in the PLS in order to measure the characteristics of the structure. The experimental results agree well with the simulations and show the validity of the modeling for the proposed PLS.

This paper proposes a novel dual-mode ring bandpass filter (BPF) using defect ground structure (DGS). The proposed filter provides wide stopband characteristic resulted from the bandgap characteristic of DGS for suppressing spurious response of the dual-mode ring BPF. The H shaped DGS cell is modeled as a parallel LC resonator and the equivalent circuit parameters are extracted. The relationship between bandgap characteristic and design parameters of DGS dimension is discussed and the bandgap characteristic of DGS on the filter performance is also investigated. The novel proposed filter has the frequency characteristics with a central frequency f0 = 7.7 GHz, a 3-dB bandwidth of 4.5% and wider stopband from 9 to 15.5 GHz at the level of -35 GHz. Measured results of experimental filter has good agreement with the theoretical simulation results.

This investigation proposes a novel dual-mode patch bandpass filter (BPF) that uses defect ground structure (DGS) to suppress spurious response. The proposed dual-mode patch BPF has exhibits a wide stopband characteristic owing to that uses the bandgap resonant characteristic of DGS in the harmonic frequency of the dual-mode patch BPF. The novel proposed filter demonstrates the frequency characteristics with center frequency f0 = 2.2 GHz, 3-dB bandwidth (FBW) of 8% and wider stopband from 2.6 to 6 GHz at the level of -35 dB. The experimental and simulated results agree.

As we enter the deep submicron era, the costs to maintain the quality of shipped products increases significantly. Unfortunately, even 100% coverage of the widely used single stuck-at faults cannot guarantee that the defect level of the shipped chips is low enough. This is due to the fact that the stuck-at fault model does not cover all catastrophic defects. Moreover, it is difficult to estimate the difference between stuck-at fault coverage and defect coverage. Multiple fault models or test techniques are usually adopted in the test process, each having its corresponding fault coverage. However, the relationship between the defect level and those individual fault coverages remains to be explored. In this paper, we first propose the concept of multi-model fault coverage (MFC) instead of the fault coverage based on a single fault model. The multi-model fault coverage for nonequiprobable faults is presented, and the multi-model fault coverage for equiprobable faults is shown to be a special case of nonequiprobable faults. The relationship between defect level, fabrication yield, and multi-model fault coverage is then derived. We also analyze the defect level error between the predicted defect level and the physical defect level. An algorithm is also proposed for estimating the number of fault models required in order to achieve sufficient accuracy. Experimental results show that multi-model fault coverage can be used to predict the defect level more precisely. As the number of fault models increases, the defect level error reduces significantly. Our approach is efficient for product quality prediction, especially for deep sub-micron devices.

This paper proposes a new supply current test method for detecting floating gate defects in CMOS ICs. In the method, unusual increase of the supply current caused by defects is promoted by superposing an AC component on the DC power supply. Feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional supply current test.

We present an overview of our work on the application of scanning near-field optical microscopy (SNOM) to photonic crystal structures. Our results show that SNOM can be used to map the subwavelength confinement of light to a point-defect in a 2D photonic crystal microresonator. Comparison with numerical modelling shows that SNOM is able to resolve patterns in the intensity distribution that are due to the slight non-uniformity in the crystal structure. We also discuss the future possibilities for applications of different modes of SNOM to photonic crystal devices.

This letter presents a novel two-dimensional (2-D) defected ground array (DGA) for planar circuits, which has horizontal and vertical periodicities of defect structure. The defect unit cell of DGA is composed of a Sierpinski carpet structure to improve the effective inductance. Measurements show that the proposed DGA provides steeper cutoff characteristics, lower cutoff frequency, and higher slow-wave factors than the conventional periodic defected ground structure in the same occupied surface.

This paper describes the performance improvement of power amplifiers by defected ground structure (DGS). Due to the excellent capability of harmonic rejection and tuning, DGS plays a great role in improving the major nonlinear behaviors of power amplifier such as output power, harmonics, power added efficiency (PAE), and the ratio between the carrier and the third order intermodulation distortion (C/IMD3). In order to verify the improvement of performances by DGS, measured data for a power amplifier, which adopts a 30 Watts LDMOS device for the operation at 2.1-2.2 GHz, are illustrated under several operating bias currents for two cases, i.e., with and without DGS attached. The principle of the improvement is described by the simple Volterra nonlinear transfer functions with the consideration of different operating classes. The obtained improvement of the 30 Watts power amplifier, under 400 mA of IdsQ as an example, includes the reduction in the second and third harmonics by 17 dB and 20 dB, and the increase in output power, PAE, and C/IMD3 by 1.3 Watts, 3.4%, and 4.7 dB, respectively.

In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.

In this paper, a new test method is proposed for detecting open defects in CMOS logic ICs. The method is based on supply current of ICs generated by supplying time-variable supply voltage and electric field from the outside of the ICs. Also, test input vectors for the test method are proposed and it is shown that they can be generated more easily than functional test methods based on stuck-at fault models. The feasibility of the test is examined by some experiments. The empirical results promise us that by using the method, open defects in CMOS ICs can be detected.

We have developed and demonstrated a novel technique for electrical inspection and electrical failure analysis, which can detect open, high-resistance, and short circuits without the need for electrical contact with the outside of the LSI chip or the board on which the LSI chip is mounted. The basic idea of the technique is the detection of the magnetic field produced by OBIC (optical beam induced current) or photo current. A DC-SQUID (superconducting quantum interference device) magnetometer is used to detect the magnetic field. This scanning laser-SQUID microscopy ("laser-SQUID" for short) has a spatial resolution of about 1.3 µm. It can be used to distinguish defective chips before bonding pad patterning or after bonding without pin-selection. It can localize any defective site in the chip to within a few square microns.

We investigate the engineering of the impurity bands in photonic crystals (PCs) for realizing high-efficiency wave guiding, all-optical switching and optical delay for ultrashort optical pulses. It is found that quasi-flat impurity bands suitable for the transmission of ultrashort pulses can be achieved by properly controlling the configuration of coupled cavity waveguides (CCWs). At sharp corners, high bending efficiency is obtained over the entire impurity band. All-optical switching can be realized by creating a dynamical band gap at the center of an impurity band. The concentration of electromagnetic wave at defect regions leads to high switching efficiency while the tunable feature of PC defects makes all-optical control possible. It is also revealed that CCWs with quasi-flat impurity bands provide efficient group delay for ultrashort pulses with negligible attenuation and distortion. From the viewpoint of practical fabrication, the effect of disorder on the transmission property of impurity bands is discussed and the criterion for localization transition is determined.

An optimal allocation model for the sub-processing-element (sub-PE) level redundancy is developed, which is solved by the genetic algorithms. In the allocation model, the average defect density D and the parameter δ are also considered in order to accurately analyze the element yield, where δ is defined as the ratio of the support circuit area to the total area of a PE. When the PE's area is imposed on the constraint, the optimal solutions of the model with different D and δ are calculated. The simulation results indicate that, for any fixed average defect density D, both the number of the optimal redundant sub-circuit added into a PE and the PE's yield decrease as δ increases. Moreover, for any fixed parameter δ, the number of the optimal redundant sub-circuit increases, while the optimal yield of the PE decreases, as D increases.