In this paper, a low power current protection circuit implemented in a low dropout regulator (LDO) is presented. The proposed circuit, designed in a 0.35 µm CMOS process, provides a precise limiting current as well as holding current with low dependency on both supply voltage and regulator output voltage. The experimental results showed that the proposed circuit is operable in the regulator output voltage range from VOUT=1.2 V to VOUT=3.6 V and supply voltage range from VDD=VOUT+0.5 V to VDD=5.6 V. Since the proposed circuit is composed of few simple basic circuits such as a comparator and a Schmitt Trigger, it has a low current consumption of less than ISS=0.82 µA at a load current of ILOAD=200 mA. This makes the circuit suitable for low power and low voltage LDO design.

In this paper, an ER (Error-Reduction) algorithm-based method for removal of adherent water drops from images obtained by a rear view camera mounted on a vehicle in rainy conditions is proposed. Since Fourier-domain and object-domain constraints are needed for any ER algorithm-based method, the proposed method introduces the following two novel constraints for the removal of adherent water drops. The first one is the Fourier-domain constraint that utilizes the Fourier transform magnitude of the previous frame in the obtained images as that of the target frame. Noting that images obtained by the rear view camera have the unique characteristics of objects moving like ripples because the rear view camera is generally composed of a fish-eye lens for a wide view angle, the proposed method assumes that the Fourier transform magnitudes of the target frame and the previous frame are the same in the polar coordinate system. The second constraint is the object-domain constraint that utilizes intensities in an area of the target frame to which water drops have adhered. Specifically, the proposed method models a deterioration process of intensities that are corrupted by the water drop adhering to the rear view camera lens. By utilizing these novel constraints, the proposed ER algorithm can remove adherent water drops from images obtained by the rear view camera. Experimental results that verify the performance of the proposed method are represented.

In a low dropout (LDO) linear regulator whose reference voltage is supplied by a bandgap reference, double stacked diodes increase the effective junction area ratio in the bandgap reference, which significantly lowers the output spectral noise of the LDO. A low noise LDO with the area-efficient bandgap reference is implemented in 0.18 µm CMOS. An effective diode area ratio of 105 is obtained while the actual silicon area is saved by a factor of 4.77. As a result, a remarkably low output noise of 186 nV/sqrt(Hz) is achieved at 1 kHz. Moreover, the dropout voltage, line regulation, and load regulation of the LDO are measured to be 0.3 V, 0.04%/V, and 0.46%, respectively.

This letter derives the packet error rate (PER) in terms of the retry limit and the channel error probability in wireless local area networks (WLANs), when an additional number of retries is allocated to a block of packets to be transmitted. We prove that the lower bound of the PER is the dropping probability which is defined as the probability of any given packet being dropped after its retry limit has been reached.

The authors present R2Power, an effective approach to the realizable reduction of RC networks with independent current sources. The proposed approach is based on the entrywise perturbation theory for diagonally dominant M-matrices. The accuracy of the node voltages of the reduced network, as compared to those of the original network, is maintained on the order of the entrywise perturbation performed during reduction. R2Power can be used to reduce the size of RC networks used to model the power networks of SoCs, for efficient IR-drop analysis. Experiments showed that R2Power reduced the size of industrial examples by more than 95%, with maximum relative node voltage errors of less than 0.012%.

With the advent of the deep submicron age, circuit performance is strongly impacted by process variations and the influence on the circuit delay to the power-supply voltage increases more and more due to CMOS feature size shrinkage. Power grid optimization which considers the timing error risk caused by the variations and IR drop becomes very important for stable and hi-speed operation of system-on-chip. Conventionally, a lot of power grid optimization algorithms have been proposed, and most of them use IR drop as their object functions. However, the IR drop is an indirect metric and we suspect that it is vague metric for the real goal of LSI design. In this paper, first, we propose an approach which uses the "timing error risk caused by IR drop" as a direct objective function. Second, the critical path map is introduced to express the existence of critical paths distributed in the entire chip. The timing error risk is decreased by using the critical path map and the new objective function. Some experimental results show the effectiveness.

It's a trend to consider the power supply integrity at early stage to improve the design quality. Specifically, floorplanning process is modified to improve the power supply as well. In the modified floorplanning process, both the floorplan and power/ground (P/G) network are adjusted to search for optimal floorplan as well as the most robust power supply. In this paper, we propose a novel algorithm to carry out this modified floorplanning. A new analytical method is proposed to estimate the voltage drop while the floorplan is varying constantly. This fast analytical voltage drop estimating method is plugged into the modified floorplanner to speed up the whole floorplanning process. Compared with previous methods, our algorithm can search for the optimal floorplan with consideration of power supply integrity more efficiently and therefore leads to better results. Furthermore, this paper also proposes a novel heuristic method to optimize the topology of P/G network. This optimization algorithm could construct a more robust power supply system. Experimental results show the method can speedup the IR-drop aware floorplanning process by about 10 times and reduce the routing area of P/G network while maintaining the floorplan quality and power supply integrity.

The electrostatic force required for the driving of liquid droplet injected in a microchannel was studied to obtain the guiding principle to reduce the driving voltage of waveguide optical switch based on the movement of droplet. We analytically calculated the relation between the threshold voltage and velocity of droplet and the surface roughness of microchannel, and clarified some unconfirmed parameters by comparing experimental results and aeromechanical analysis. The driving of droplet in a microchannel was best analyzed using the Hagen-Poiseuille flow theory, taking into account the movement of both ends of the droplet. When the droplet is driven by some external force, a threshold of the external force occurs in the starting of movement, and hysteresis occurs in the contact angle of the droplet to the side wall of the microchannel. The hysteresis of contact angle is caused by the roughness of side wall. In our experiment, the threshold voltage ranged from 200 to 350 V and the switching time from 34 to 36 ms. The velocity of droplet was evaluated to be 0.3-0.4 mm/s from these experimental results. On the other hand, the measured angle distribution of side wall roughness ranged from 30 to 110 degrees, and the threshold voltage was evaluated to be 100-320 V, showing a good agreement with experimental results. The reduction of threshold voltage can be realized by smoothing the side wall roughness of microchannel. The switching time of 10 ms, which is required for the optical stream switch, can be obtained by shortening the horizontal spot size down to 1.5 µm.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

Due to the dynamics of topology and resources, Call Admission Control (CAC) plays a significant role for increasing resource utilization ratio and guaranteeing users' QoS requirements in wireless/mobile networks. In this paper, a dynamic multi-threshold CAC scheme is proposed to serve multi-class service in a wireless/mobile network. The thresholds are renewed at the beginning of each time interval to react to the changing mobility rate and network load. To find suitable thresholds, a reward-penalty model is designed, which provides different priorities between different service classes and call types through different reward/penalty policies according to network load and average call arrival rate. To speed up the running time of CAC, an Optimized Genetic Algorithm (OGA) is presented, whose components such as encoding, population initialization, fitness function and mutation etc., are all optimized in terms of the traits of the CAC problem. The simulation demonstrates that the proposed CAC scheme outperforms the similar schemes, which means the optimization is realized. Finally, the simulation shows the efficiency of OGA.

It is well known that there is relationship between electromagnetic emanation and processing information in IT devices such as personal computers and smart cards. By analyzing such electromagnetic emanation, eavesdropper will be able to get some information, so it becomes a real threat of information security. In this paper, we show how to estimate amount of information that is leaked as electromagnetic emanation. We assume the space between the IT device and the receiver is a communication channel, and we define the amount of information leakage via electromagnetic emanations by its channel capacity. By some experimental results of Tempest, we show example estimations of amount of information leakage. Using the value of channel capacity, we can calculate the amount of information per pixel in the reconstructed image. And we evaluate the effectiveness of Tempest fonts generated by Gaussian method and its threshold of security.

Stochastic approaches for effective power distribution network optimization are proposed. Considering node voltages obtained using dynamic voltage drop analysis as sample variables, multi-variate regression is conducted to optimize clock timing metrics, such as clock skew or jitter. Aggregate correlation coefficient (ACC) which quantifies connectivity between different chip regions is defined in order to find a possible insufficiency in wire connections of a power distribution network. Based on the ACC, we also propose a procedure using linear regression to find the most effective region for improving clock timing metrics. By using the proposed procedure, effective fixing point were obtained two orders faster than by using brute force circuit simulation.

In this review paper we showcase recent activities on silicon photonics science and technology research in Hong Kong regarding two important topical areas--microresonator devices and optical nonlinearities. Our work on silicon microresonator filters, switches and modulators have shown promise for the nascent development of on-chip optoelectronic signal processing systems, while our studies on optical nonlinearities have contributed to basic understanding of silicon-based optically-pumped light sources and helium-implanted detectors. Here, we review our various passive and electro-optic active microresonator devices including (i) cascaded microring resonator cross-connect filters, (ii) NRZ-to-PRZ data format converters using a microring resonator notch filter, (iii) GHz-speed carrier-injection-based microring resonator modulators and 0.5-GHz-speed carrier-injection-based microdisk resonator modulators, and (iv) electrically reconfigurable microring resonator add-drop filters and electro-optic logic switches using interferometric resonance control. On the nonlinear waveguide front, we review the main nonlinear optical effects in silicon, and show that even at fairly modest average powers two-photon absorption and the accompanied free-carrier linear absorption could lead to optical limiting and a dramatic reduction in the effective lengths of nonlinear devices.

Service differentiation is one of the key issues in the current Internet. In this paper, we focus on a recent proposal for proportional loss rate differentiation which employs a single FIFO queue, an AQM algorithm for computing the packet drop probability, and a counter-based packet dropping routine for achieving the intended proportional loss rate differentiation among classes. It is first shown that, when the target dropping probability of a class is large, the counter-based packet dropping routine may yield a significant amount of error between the target and measured drop probabilities for the class, and subsequently, fails to maintain the loss rate ratios between classes as intended. To avoid this problem, a new compensatory packet dropping routine is developed in this paper. Then, a series of simulation experiments are conducted using the ns-2 simulator to assess the performances of the two dropping routines under various congestion conditions and quality spacings between classes. The simulation results show that, unlike the counter-based dropping routine, the proposed compensatory dropping routine is effective in keeping the loss rate ratios between classes closely on target regardless of the degree of congestion and quality spacing between classes, while the two dropping routines perform similarly in terms of throughput and queueing delay in the bottleneck link. In addition, such robustness of the proposed routine is achieved without any additional control parameter or computational effort compared to the counter-based routine.

High power dissipation can occur when the response to a test vector is captured by flip-flops in scan testing, resulting in excessive IR drop, which may cause significant capture-induced yield loss in the DSM era. This paper addresses this serious problem with a novel test generation method, featuring a unique algorithm that deterministically generates test cubes not only for fault detection but also for capture power reduction. Compared with previous methods that passively conduct X-filling for unspecified bits in test cubes generated only for fault detection, the new method achieves more capture power reduction with less test set inflation. Experimental results show its effectiveness.

We propose an N-channel power-compensated reconfigurable optical add/drop multiplexer (ROADM) based on using fiber Bragg gratings (FBGs). Both tunable FBGs and wavelength-fixed FBGs are used in this ROADM. By using the dual-pass amplification scheme with two pieces of erbium doped fibers, an 8.0 dB optical net gain has been achieved with a gain variation less than 0.5 dB for each add/drop/pass-through channel. System performance was studied for a four-WDM-channel 10 Gb/s100-km lightwave transmission trial network and bit error rate of 10-9 is observed for the 50 km added signal, 100 km pass-through signal and 50 km dropped signal at -18.3, -19.4 and -18.9 dBm received power, respectively. Only 1.1 dB of power penalty was observed compared to the back-to-back transmission.

We propose and experimentally demonstrate a simple method for monitoring optical signal-to-noise ratio. The novel method can be used in the optical transport networks using optical cross-connects or reconfigurable optical add-drop multiplexers. OSNR is measured by monitoring the transmitted optical power and the reflected optical power from fiber Bragg grating. We have obtained OSNR with an error less than 0.8 dB.

We report on a channel drop filter with a mode gap in the propagating mode of a photonic crystal slab that was fabricated on silicon on an insulator wafer. The results, simulated with the 3-dimensional finite-difference time-domain and plane-wave methods, demonstrated that an index-guiding mode for the line defect waveguide of a photonic crystal slab has a band gap at wave vector k = 0.5 for a mainly TM-like light-wave. The mode gap works as a distributed Bragg grating reflector that propagates the light-wave through the line defect waveguide, and can be used as an optical filter. The filter bandwidth was varied from 1-8 nm with an r/a (r: hole radius, a: lattice constant) variation around the wavelength range of 1550-1600 nm. We fabricated a Bragg reflector with a photonic crystal line-defect waveguide and Si-channel waveguides and by measuring the transmittance spectrum found that the Bragg reflector caused abrupt dips in transmittance. These experimental results are consistent with the results of the theoretical analysis described above. Utilizing the Bragg reflector, we fabricated channel dropping filters with photonic crystal slabs connected between channel waveguides and demonstrated their transmittance characteristics. They were highly drop efficient, with a flat-top drop-out spectrum at a wavelength of 1.56 µm and a drop bandwidth of 5.8 nm. Results showed that an optical add-drop multiplexer with a 2-D photonic crystal will be available for application in WDM devices for photonic networks and for LSIs in the near future.

Accurate on-chip 100-ps/100-µV waveform measurements of signal transition in a large-scale digital integrated circuit clearly demonstrates the correlation of dynamic delay variation with power supply noise waveforms. In addition to the linear dependence of delay increase with the height of static IR drop, the distortion of a signal waveform during a logic transition that is induced by dynamic power supply noise causes significant delay variation. However, an analysis reveals that average modeling of dynamic power supply noise, which is often used in conventional simulation techniques, cannot match the experimentally measured values. Our proposed circuit simulation technique, which incorporates time-domain power supply noise waveform macro models along with parasitic impedance networks, reproduces the delay variation well, even with a relative timing difference among different clock domains. Such basic knowledge can be applied in precise delay calculations that consider dynamic power supply noise, a crucial factor in deep sub-100-nm LSI design.

We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.