This paper presents deep learning to recognize online handwritten mathematical symbols. Recently various deep learning architectures such as Convolution neural networks (CNNs), Deep neural networks (DNNs), Recurrent neural networks (RNNs) and Long short-term memory (LSTM) RNNs have been applied to fields such as computer vision, speech recognition and natural language processing where they have shown superior performance to state-of-the-art methods on various tasks. In this paper, max-out-based CNNs and Bidirectional LSTM (BLSTM) networks are applied to image patterns created from online patterns and to the original online patterns, respectively and then combined. They are compared with traditional recognition methods which are MRFs and MQDFs by recognition experiments on the CROHME database along with analysis and explanation.

SUMMARY This paper proposes a power-supply-noise-aware timing analysis and test pattern regeneration framework suitable for testing 3D IC. The proposed framework analyzes timing with reasonable accuracy at much faster speed than existing tools. This technique is very scalable because it is based on analytical functions, instead of solving nonlinear equations. The experimental results show, for small circuits, the error is less than 2% compared with SPICE. For large circuits, we achieved 272 times speed up compared with a commercial tool. For a large benchmark circuit (638K gates), we identified 88 risky patterns out of 31K test patterns. We propose a test pattern regeneration flow to replace those risky patterns with very little (or even no) penalty in fault coverage. Our test sets are shorter than commercial power-aware ATPG while the fault coverage is almost the same as power-unaware ATPG.

Excessive IR-drop in capture mode during at-speed scan testing may cause timing errors for defect-free circuits, resulting in undue test yield loss. Previous solutions for achieving capture-power-safety adjust the switching activity around logic paths, especially long sensitized paths, in order to reduce the impact of IR-drop. However, those solutions ignore the impact of IR-drop on clock paths, namely test clock stretch; as a result, they cannot accurately achieve capture-power-safety. This paper proposes a novel scheme, called LP-CP-aware ATPG, for generating high-quality capture-power-safe at-speed scan test vectors by taking into consideration the switching activity around both logic and clock paths. This scheme features (1) LP-CP-aware path classification for characterizing long sensitized paths by considering the IR-drop impact on both logic and clock paths; (2) LP-CP-aware X-restoration for obtaining more effective X-bits by backtracing from both logic and clock paths; (3) LP-CP-aware X-filling for using different strategies according to the positions of X-bits in test cubes. Experimental results on large benchmark circuits demonstrate the advantages of LP-CP-aware ATPG, which can more accurately achieve capture-power-safety without significant test vector count inflation and test quality loss.

We propose a simple configuration for colorless and directionless (CD) reconfigurable optical add/drop multiplexers that enables ultra-low contention add/drop operation to be achieved. In the configuration, we apply a combination of multiple small-port-count CD add/drop banks (CD banks) and round-robin CD bank assignment. Evaluation results show that the proposed configuration can substantially reduce intra-node contention rate, which is less than 0.1%. We also find that the proposed configuration can improve the utilization efficiency of wavelength resources and transponders. We discuss the mechanism of how the proposed configuration reduces intra-node contention by analyzing the status of wavelength assignments in direction ports and CD banks.

The applicability of at-speed scan-based logic built-in self-test (BIST) is being severely challenged by excessive capture power that may cause erroneous test responses even for good circuits. Different from conventional low-power BIST, this paper is the first to explicitly focus on achieving capture power safety with a novel and practical scheme, called capture-power-safe logic BIST (CPS-LBIST). The basic idea is to identify all possibly-erroneous test responses caused by excessive capture power and use the well-known approach of masking (bit-masking, slice-masking,vector-masking) to block them from reaching the multiple-input signature register(MISR). Experiments with large benchmark circuits and a large industrial circuit demonstrate that CPS-LBIST can achieve capture power safety with negligible impact on test quality and circuit overhead.

A mobile hotspot is a moving vehicle that hosts an Access Point (AP) such as train, bus and subway where users in these vehicles connect to external cellular network through AP to access their internet services. To meet Quality of Service (QoS) requirements, typically throughput and/or delay, a Call Admission Control (CAC) is needed to restrict the number of users accepted by the AP. In this paper, we analyze a modified guard channel scheme as CAC for mobile hotspot as follows: During a mobile hotspot is in the stop-state, we adopt a guard channel scheme where the optimal number of resource units is reserved for vertical handoff users from cellular network to WLAN. During a mobile hotspot is in the move-state, there are no handoff calls and so no resources for handoff calls are reserved in order to maximize the utility of the WLAN capacity. We model call's arrival and departure processes by Markov Modulated Poisson Process (MMPP) and then we model our CAC by 2-dimensional continuous time Markov chain (CTMC) for single traffic and 3-dimensional CTMC for two types of traffic. We solve steady-state probabilities by the Quasi-Birth and Death (QBD) method and we get various performance measures such as the new call blocking probabilities, the handoff call dropping probabilities and the channel utilizations. We compare our CAC with the conventional guard channel scheme which the number of guard resources is fixed all the time regardless of states of the mobile hotspot. Finally, we find the optimal threshold value on the amount of resources to be reserved for the handoff call subject to a strict constraint on the handoff call dropping probability.

In this paper, we propose periodic and aperiodic security limits for compromising emanations in the VHF and UHF bands. First, we perform the electromagnetic emanation security (EMSEC)-channel measurements in the 200-1000MHz frequency bands. Second, we analyse the pathloss characteristics of the indoor EMSEC-channel based on these measurements. Through this EMSEC-channel analysis, we affirm that the total radio attenuation, which is one of the key parameters for determining the security limits for compromising emanations, follows the Rician distribution. With these results, we propose that periodic and aperiodic emission security limits can be classified into two levels depending on the total radio attenuation and the extent of required confidentiality. The proposed security limits are compared with other security limits and existing civil and military EMC standards.

Test power has become a critical issue, especially for low-power devices with deeply optimized functional power profiles. Particularly, excessive capture power in at-speed scan testing may cause timing failures that result in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. However, previous capture-safety checking metrics suffer from inadequate accuracy since they ignore the time relations among different transitions caused by a test vector in a circuit. This paper presents a novel metric called the Transition-Time-Relation-based (TTR) metric which takes transition time relations into consideration in capture-safety checking. Detailed analysis done on an industrial circuit has demonstrated the advantages of the TTR metric. Capture-safety checking with the TTR metric greatly improves the accuracy of test vector sign-off and low-capture-power test generation.

An active queue management (AQM) scheme is proposed to reduce throughput bias for UDP flows over TCP. It is argued that existing AQM methods partially involve a flow-indifferent factor that does not take into account of bandwidth usage of flows when they determine packet drop, thus resulting in unfairness. The proposed scheme replaces the flow-indifferent part with a flow-wise one by approximating per-flow fair share, which permits the discrimination of unresponsive flows. Since it is a stateless process, it avoids the overhead of tracking the statistics of flows and implementation is simple. A performance evaluation shows that it effectively limits the bandwidth of unresponsive flows to their fair share of bandwidth. In addition, it can also encourage RTT-fairness among TCP flows with different delays.

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18 µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6 V. The designed IA achieves 30 dB of closed-loop gain, 101 dB of common-mode rejection ratio (CMRR) at 50 Hz, 80 dB of power-supply rejection ratio (PSRR) at 50 Hz, thermal noise floor of 53.4 nV/, current consumption of 14 µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6 V supply from a 0.8–1.0 V energy harvesting power source. It achieves power supply rejection (PSR) of 42 dB at frequency of 1 MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6 dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100 Hz sinusoidal maximum input signal, bandwidth of 2 kHz, and power consumption of 51.2 µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18 µm CMOS process.

Low drop-out regulators (LDOs) are widely used in the system-on-a-chip (SoC) design. Due to the multi-function and energy saving requirements for mobile applications nowadays, more strict specifications are expected on the developmental roadmap of the LDOs. An output-capacitorless LDO providing fast transient response under the low supply voltage and low quiescent current conditions is proposed in this paper. Provided by the low supply voltage, the proposed LDO adopts cascading technique using the Multipath Nested Miller Compensation (MNMC) to maintain a higher bandwidth for fast transient requirement. In addition, a Transient Quiescent Current Booster (TQCB) is supplemented to the operational amplifier to improve the slew rate for the fast load transient. The TQCB only raises the quiescent current during the load transient instant so that both power saving and the load response improvement could be well achieved. It deserves noting that the proposed TQCB contains only two transistors, which is simple to be implemented compared to the other transient current enhancement techniques. The designed LDO has only 1.6 pF capacitance for the totally added on-chip compensation, and 25.8 µA of current consumption in the main amplifier. The recovery time under the fast load change is less than 3 µs and the stability is guaranteed. Test results from the real implementation of a 0.35 µm CMOS process verify that the designed LDO performs as expected.

Multiple-attribute based handoff schemes suffer from instability because of the dynamic nature of attributes and the distribution of handoff procedure over candidate networks, resulting in frequent handoffs that degrade the efficiency of resource management. To alleviate such instability, a service-history based scheme was proposed but it has several improper design decisions, e.g. it considers the history factors too optimistically and employs fixed weights that are likely to distort handoff decisions. This letter proposes to improve handoff performance by considering network state along with the service history. It takes into account the network utilization to avoid the optimistic dependency on the history and adaptively determines the weight to the service history in order to adjust its effect on the handoff decision. Simulation results show that the proposed scheme optimizes the number of handoff and the dropping probability when compared with existing schemes.

This paper introduces a hard handover strategy with a novel adaptive hysteresis adjustment that is needed to reduce handover drop rate in 3GPP long term evolution (LTE). First of all, we adopt a Hybrid handover scheme considering both the received signal strength (RSS) and the load information of the adjacent evolved Node Bs (eNBs) as a factor for deciding the target eNB. The Hybrid scheme causes the load status between the adjacent eNBs to be largely similar. Then, we propose a modified load-based adaptive hysteresis scheme to find a suitable handover hysteresis value utilizing the feature of the small load difference between the target and serving eNBs obtained from the result of the Hybrid scheme. As a result, through the proposed modified load-based adaptive hysteresis scheme, the best target cell is very well selected according to the dynamically changing communication environments. The simulation results show that the proposed scheme provides good performance in terms of handover drop rate.

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-µA quiescent current at 200-µA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

We propose a compact matrix-switch-based hierarchical optical cross-connect (HOXC) architecture that effectively handles the colorless waveband add/drop ratio restriction so as to realize switch scale reduction. In order to implement the colorless waveband add/drop function, we develop a wavelength MUX/DMUX that can be commonly used by different wavebands. We prove that the switch scale of the proposed HOXC is much smaller than that of conventional single-layer optical cross-connects (OXCs) and a typical HOXC. Furthermore, we introduce a prototype system based on the proposed architecture that utilizes integrated novel wavelength MUXs/DMUXs. Transmission experiments prove its technical feasibility.

Power-aware X-filling is a preferable approach to avoiding IR-drop-induced yield loss in at-speed scan testing. However, the ability of previous X-filling methods to reduce launch switching activity may be unsatisfactory, due to low effect (insufficient and global-only reduction) and/or low scalability (long CPU time). This paper addresses this reduction quality problem with a novel GA (Genetic Algorithm) based X-filling method, called GA-fill. Its goals are (1) to achieve both effectiveness and scalability in a more balanced manner and (2) to make the reduction effect of launch switching activity more concentrated on critical areas that have higher impact on IR-drop-induced yield loss. Evaluation experiments are being conducted on both benchmark and industrial circuits, and the results have demonstrated the usefulness of GA-fill.

In a typical SoC (System-on-Chip) design, a huge peak current often occurs near the time of an active clock edge because of aggregate switching of a large number of transistors. The number of aggregate switching transistors can be lessened if the SoC design can use a clock scheme of mixed rising and falling triggering edges rather than one of pure rising (falling) triggering edges. In this paper, we propose a clock-triggering-edge assignment technique and algorithms that can assign either a rising triggering edge or a falling triggering edge to each clock of each IP core of a given IP-based SoC/NoC (Network-on-Chip) design. The goal of the algorithms is to reduce the peak current of the design. Our proposed technique has been implemented as a software system. The system can use an LP technique to find an optimal or suboptimal solution within several seconds. The system also can use an ILP technique to find an optimal solution, but the ILP technique is not suitable to be used to solve a complex design. Experimental results show that our algorithms can reduce peak currents up to 56.3%.

This paper describes the design methodology of a low dropout regulator (LDO). It was used to develop a power management sub-system IC for CDMA handsets which is also described in this paper. This IC contains 11 LDOs, bandgap reference, battery charger, control logic and some other peripheral circuits. For CDMA applications, very small ground current in the order of µA in standby mode is required for LDOs. An LDO architecture to meet this requirement and achieve stable operation over the process variation was developed. The on-chip logic efficiently controls all LDOs and battery charger to reduce the power dissipation as much as possible. This mixed signal subsystem has been implemented in the in-house 0.6-µm BCDMOS process. The very low LDO ground current down to 3 µA has been achieved with stable operation.

In an early design stage of LSI designing, finding out the proper parameters for power planning is important from the viewpoint of cost minimization. In this paper, we present simple analytical formulas which are used to obtain the initial parameters close to the proper power distribution networks in the early design stage. The formulas for estimating static and pseudo-dynamic voltage drops (IR-drops) are derived by the response surface method (RSM). By making the formulas once, they can be used for the general power planning for the power-grid style in any process technology.

A time-slicing ring oscillator (TSRO) which captures time-dependent delay degradation due to periodic transient voltage drop on a power supply network is proposed. An impact of the supply voltage fluctuations, including voltage drop and overshoot, on logic circuit delay is evaluated as a change of oscillation frequency. The TSRO is designed using standard logic cells so that it can be placed almost anywhere in a digital circuit wherein supply voltage fluctuation is concerned. We also propose a new procedure for reconstructing supply voltage waveform. The procedure enables us to accurately monitor time-dependent, effective supply voltages. The -1 dB bandwidth of the TSRO is simulated to be 15.7 GHz, and measured time resolution is 131 ps. Measurement results of a test chip using 90-nm standard CMOS process successfully proved the feasibility of both delay degradation and effective supply voltage fluctuation measurements. Measurement of spatial voltage drop fluctuation is achieved.