This paper proposes a novel differential active self-interference canceller (DASIC) algorithm for asynchronous in-band full-duplex (IBFD) Gaussian filtered frequency shift keying (GFSK), which is designed for wireless Internet of Things (IoT). In IBFD communications, where two terminals simultaneously transmit and receive signals in the same frequency band, there is an extremely strong self-interference (SI). The SI can be mitigated by an active SI canceller (ASIC), which subtracts an interference replica based on channel state information (CSI) from the received signal. The challenging problem is the realization of asynchronous IBFD for wireless IoT in indoor environments. In the asynchronous mode, pilot contamination is induced by the non-orthogonality between asynchronous pilot sequences. In addition, the transceiver suffers from analog front-end (AFE) impairments, such as phase noise. Due to these impairments, the SI cannot be canceled entirely at the receiver, resulting in residual interference. To address the above issue, the DASIC incorporates the principle of the differential codec, which enables to suppress SI without the CSI estimation of SI owing to the differential structure. Also, on the premise of using an error correction technique, iterative detection and decoding (IDD) is applied to improve the detection capability while exchanging the extrinsic log-likelihood ratio (LLR) between the maximum a-posteriori probability (MAP) detector and the channel decoder. Finally, the validity of using the DASIC algorithm is evaluated by computer simulations in terms of the packet error rate (PER). The results clearly demonstrate the possibility of realizing asynchronous IBFD.

Smaller antenna structures for long-range radar transmitters and receivers operating in the 77-GHz band for automotive application have been achieved by using antennas with a horn, lens, and microstrip antenna. The transmitter (Tx) antenna height was reduced while keeping the antenna gain high and the antenna substrate small by developing an antenna structure composed of two differential horn and lens antennas in which the diameter and focus distance of the lenses were half those in the previous design. The microstrip antennas are directly connected to the differential outputs of a monolithic microwave integrated circuit. A Tx antenna fabricated using commercially available materials was 14mm high and had an output-aperture of 18×44mm. It achieved an antenna gain of 23.5dBi. The antenna substrate must be at least 96mm2. The antenna had a flat beam with half-power elevation and azimuth beamwidths of 4.5° and 21°, respectively. A receiver (Rx) antenna array composed of four sets of horn and lens antennas with an output-aperture of 9×22mm and a two-by-two array configuration was fabricated for application in a newly proposed small front-end module with azimuth direction of arrival (DOA) estimation. The Rx antenna array had an antenna coupling of less than -31dB in the 77-GHz band, which is small enough for DOA estimation by frequency-modulated continuous wave radar receivers even though the four antennas are arranged without any separation between their output-apertures.

This paper presents an experimental evaluation of an ocean wave remote sensing system that uses bistatic GPS signal reflection to estimate wave characteristics. In our previous paper, a bistatic ocean wave remote sensing system by GPS was proposed to estimate the characteristics of sea swell near a harbor, and was also evaluated by numerical simulations. In the next phase, a prototype system has been developed and some basic experiments have been carried out in a coastal area in order to evaluate the system experimentally. In this paper, we will outline the prototype system. The system mainly consists of an array antenna, a front-end, and an estimator for ocean wave characteristics. Next, we explain that the estimator for ocean wave characteristics can identify each signal reflected from the ocean waves. Finally, the experiments show that the prototype system can receive the reflected signals from the sea-surface near the coast, and estimate the wave period and wavelength in the direction of the array antenna.

Single front-end architecture with parasitic antenna element (PAE) in compact array system has been proposed for enhancing spectral efficiency and miniaturizing the receiver. Although most of studies paid attention to design optimal receiver with antenna mutual coupling on fading correlation, relatively little attention has been paid to noise. In this paper, we propose a low noise model for single front-end MIMO receiver system with PAE which includes arbitrary signal and noise coupling. The proposed model articulates physical noise sources and relates their spatial correlation with array receive antennas, parasitic element, front-end and matching circuit. A matching circuit is designed to achieve minimum noise figure. After that, the optimal PAE value is derived to maximize channel capacity. We present numerical analysis to verify the proposed system on certain conditions.

In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18 µm deep n-well CMOS technology and draws 12 mA from a 1.8 V supply voltage. It shows a voltage gain of 31 dB, a noise figure (NF) lower than 2.6 dB, and an IIP3 of -8 dBm from 470 MHz to 862 MHz.

In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

This paper presents a compact and highly integrated triple-band RF front-end module (FEM) for worldwide interoperability for microwave access (WiMAX) applications using multilayer low temperature co-fired ceramic (LTCC) technology. The proposed RF FEM is composed of a TX triplexer, an RX triplexer, and a TX/RX switch. Both TX and RX triplexers are fully embedded in an LTCC substrate and the TX/RX switch is placed on the substrate. The TX triplexer consists of 2- and 5-GHz lowpass filters, a 3-GHz highpass filter, and a matching circuit. On the other hand, the RX triplexer consists of miniaturized 2-, 3-, 5-GHz coupled-resonator bandpass filters and a matching circuit, which are stacked up for space saving. In TX path, the RF FEM provides an insertion loss of 1.8 dB, 2.1 dB and 2.5 dB at 2-, 3-, and 5-GHz band, respectively, with a high second-harmonic suppression characteristic. In RX path, the RF FEM also provides a low insertion loss at three passbands with high attenuation at other passbands. The size of the proposed RF FEM is only 4.0 mm5.0 mm with a substrate thickness of 0.73 mm. The measured results are in good agreement with the simulated results.

An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the effective data capacity, and for an optimal exploitation of this capacity for given power dissipation. At high level, this asks for a new view on the so-called client-server relations in the chain. To substantiate this vision, some examples of research projects in our group are addressed. These include FE-driven transmission schemes, duty-cycled operation with wake-up radio, programmable FEs, smart antenna-FE combinations, smart and flexible converters, and smart pre and post correction.

To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

This letter presents a 900 MHz ZigBee RF transmitter front-end with on-chip LO suppression circuit at the output. To suppress the LO leakage at the RF output, a novel LO suppression circuit is adopted at the up-conversion mixer. The RF transmitter implemented in 0.18 µm CMOS shows more than 28 dB of LO suppression over a wide range of the baseband signal power variation.

In order to reduce the size of a wireless system, we propose a design theory for the broadband impedance matching circuit which connects an electrically small antenna (ESA) to a semiconductor amplifier. We confirmed its validity for the case of connection between a small slot loop antenna with a small radiation resistance of Ra =0.776 Ω and a semiconductor amplifier with high input impedance of ZL =321-j871 Ω with the aid of the simulations by the electrical circuits using transmission lines as well as the electromagnetic field (EM field) simulator. We also made experiments on this antenna with matching circuits using high temperature superconductor YBCO thin films on MgO substrates.

A fully integrated RF front-end for W-CDMA applications including a low noise amplifier, a down conversion mixer, a digitally programmable gain amplifier, an on-chip VCO, and a fractional-N frequency synthesizer is designed using a 0.35-µm CMOS process. A multi-stage ring shaped on-chip LC-VCO exhibiting bandpass characteristics overcomes the limitation of low-Q components in the tank circuits and improves the phase noise performance. The measured phase noise of the on-chip VCO is -134 dBc/Hz at 1 MHz offset. The receiver RF front-end achieves a NF of 3.5 dB, an IIP3 of -16 dBm, and a maximum gain of 80 dB. The receiver consumes 52 mA with a 3-V supply and occupies only 2 mm2 die area with minimal external components.

A broadband RF front-end having a direct conversion architecture has been developed. The RF front-end consists of two broadband quadrature mixers, a multi-band local oscillator, and a broadband low-noise variable gain amplifier (LNVGA). The mixer achieves broadband characteristics through the incorporation of an in-phase power divider and a 45-degree power divider. The in-phase power divider achieves broadband characteristics through the addition of a compensation capacitor. The 45-degree power divider achieves broadband phase characteristics through the addition of a compensation capacitor and a compensation resistor. The local oscillator, which is composed of two VCOs, two frequency dividers, and four switches, can cover three systems including one FDD system. The LNVGA achieves its broadband characteristics without the use of reactance elements, such as inductors or capacitors. In a trial demonstration, when the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a demodulator experimentally demonstrated an amplitude balance of less than 1.6 dB and a quadrature phase error of less than 3 degrees. When the RF frequency was between 900 MHz and 2.5 GHz, the mixer for a modulator demonstrated an image ratio of less than -30 dBc. The local oscillator demonstrated multi-band characteristics, which are able to cover the target frequencies for three systems (PDC, PHS, 2.4 GHz WLAN). From 900 MHz to 2.5 GHz, the amplifier shows a noise figure of less than 2.1 dB and a gain of 28 1.6 dB.

We have proposed the packet SS-CDMA scheme for downlink of SS-CDMA flexible wireless cellular network. Transmission packet is framed with synchronization block with 11 chip Barker code and information block with orthogonal spreading code. The chip synchronization is carried out using short code surface acoustic wave (SAW) matched filter. The code de-spreading is carried out using in-line de-spreader. Multi-channel downlink of 63 channels can be designed using orthogonal m-sequence. Simulation results show more than 15 channels without degradation from theoretical value can be used under multi-path environment. The packet SS-CDMA modem has been implemented using a 2.4 GHz front-end SAW matched filter. Degradation of Eb/N0 of less than 0.5 dB is experimentally achieved with four-channel multiplex.

The intermediate language (IL) modularizes a compiler into target processor independent and dependent parts, called the front-end and the back-end. By adding a new back-end, it is possible to port existing software from one processor to another. This paper presents a new efficient approach to achieve multiple targeting to quite different architectures using different processors as well, by translating from one IL into other existing ILs. This approach makes it possible to reuse existing back-ends. It has been successfully applied to a commercial-scale project for porting public switching system software. Since the target ILs were not predictable in advance, we provided an abstract syntax tree (AST) with attributes accessible by abstract data type (ADT) interface to convey the source language information from our front-end to back-ends. It was translated into several ILs that were developed independently. These translations made the compiler available in a very short time for different cross-target platforms and on several workstations we needed. The structure of this AST and the mapping to these ILs are presented, and retargeting cost is evaluated.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

Large-area high-temperature superconducting films and damage-free processing techniques have been developed to fabricate low insertion loss and sharp skirt filters for mobile telecommunication. An off-axis-type dc sputtering method was employed to deposit Y-Ba-Cu-O films on both sides of the substrate. The surface resistance of the films was about 0. 35 mΩ(at 70 K and 10 GHz). An 11-pole bandpass receiving filter for the IS-95 telecommunication system was designed and fabricated using 60 mm 50 mm YBCO films on a 0. 5-mm-thick MgO substrate. The passband insertion loss at 70 K was about 0. 1 dB with 0. 1 dB ripple. The third-order intercept point of the filter was 49. 5 dBm. We have assembled the filter and a low-noise amplifier in a dewar with a cryocooler. Ultralow-noise performance (noise figure: 0. 5 dB at 70 K) was presented by the cryogenic filter subsystem.

A single-chip GaAs Transmit/Receive (T/R)-MMIC front-end has been developed which is applicable to 1. 9-GHz personal communication terminals such as digital cordless phones. This chip is fabricated using a planar self-aligned gate FET useful for low-cost and high-volume production. The chip integrates RF front-end analog circuits a power amplifier, a T/R-switch, and a low-noise amplifier. Additionally integrated are a newly developed voltage-doubler negative-voltage generator (VDNVG) and a control logic circuit to control transmit and receive functions, enabling both a single-voltage operation and an enhanced power handling capability of the switch, even under a single low-voltage supply condition of 2 V. The power amplifier incorporated onto the chip is capable of delivering a 21 dBm output power at a 39% efficiency, and a 30 dB associated gain with a 2 V single power supply in the transmit mode. The gain and efficiency are higher than those of the previously reported amplifier operating with a 2 V single power supply. The VDNVG produces a step-up voltage of 2. 9 V as well as a negative voltage of -1. 8 V from a 2 V power supply, operating with a charge time of less than 0. 25 µs. The control logic circuit on the chip has a newly designed interface circuit utilizing the step-up voltage and negative voltage, thereby enabling the chip to handle high power outputs over 24 dBm with a low operating voltage of 2 V. In the receive mode, a 1. 7 dB noise figure and a 0. 6 dB insertion loss are achieved with a current dissipation of 3. 6 mA. The developed MMIC, which is the first reported 2 V single-voltage operation T/R-MMIC front-end, is expected to contribute to the size and weight reductions in personal communication terminals.

Highly miniaturization technology in front-end GaAs Hybrid IC for mobile communication equipment will be presented. A combination of MBB (micro bump bonding) technology and the new GaAs IC fabrication process using high dielectric constant (εr) thin film technology has achieved a super small HIC with low cost and low power consumption. The new HIC was constructed of only a ceramic substrate in which the spiral inductors were formed on it and the GaAs IC chip that was bonded by using MBB technology. The MBB technology lead the HIC to a lower temperature process without soldering, a smaller bump diameter, at shorter intervals and the lowest parasitic in the bump. The advantage of the small bonding pad of the IC contributes to miniaturize the IC chip and reduces the chip cost. The GaAs IC process technology using high-εr thin film achieves the integration of all capacitors in the IC without increasing the chip size. Furthermore, low power consumption was achieved by 0. 5-µm LDD BP-MESFET with a high k-value. Although capacitors were integrated on the IC, all of the inductors were formed on the top of the ceramic substrate using a thin film metal process. This was used due to its large occupation area when it was integrated on the IC, and produced a low Q-factor. As a results, the chip was minimized to a size of 0. 81. 0 mm2 and achieved a low-cost chip. Two types of HICs were fabricated for 880 MHz cellular band and 1. 9 GHz PHS (Personal Handy phone System) band. The HIC at 880 MHz measures only 5. 05. 01. 0 mm3, and offered a conversion gain of 25 dB, a noise figure of 4. 2 dB and an image rejection ratio of 12 dB at 2. 7 V and at a power supply of 3. 5 mA. The HIC for 1. 9 GHz measures only 3. 54. 01. 0 mm3, and showed a conversion gain of 16. 0 dB, a II P3 of -16. 0 dBm, and an image rejection ratio of over 20 dBc at 3. 0 V and at power supply of 4. 5 mA.

Low-voltage technology in front-end GaAs IC for mobile communication equipment will be presented. New techniques in combination with different threshold voltage (Vth) FETs for an amplifier and a mixer were investigated for low-voltage operation of the IC. The amplifier and mixer consist of a cascode connected to FETs with shallow and deep Vth. The best suitable distribution of the supply voltages was accomplished for each FETs by using a combination of different Vth, and excellent RF characteristics of the IC were obtained, even at low voltage operation. In addition, this front-end IC has a high image rejection ratio (IRR) without using an external image rejection filter, but by using high Q-value input and intermediate matching circuits. The fabrication process used an asymmetric self-aligned BP-LDD process and high dielectric constant (high-εr) on-chip bypass capacitors using SrTiO3 contributed to a reduction in dissipation current, chip size and parasitic reactance in the source wires. The fabricated IC showed a conversion gain (CG) of 23 dB, noise figure (NF) of 2.8 dB, 3rd order output intercept point (IP3out) of 3 dBm, image rejection ratio (IRR) over 20 dBc and LO to RF isolation over 25 dB, operating by 1.0 V single supply with dissipation current of 6.8 mA at 880 MHz. At 1.9 GHz, the IC also showed excellent RF characteristics with dissipation current of 6.5 mA at 1.0 V. The IC die is very small the size is 0.75 mm0.75 mm, and is molded in a mini-6pin plastic package.