Sector antennas provide many advantages such as when combined with a narrow beam antenna, they become particularly effective in achieving high-speed wireless communication systems and they aid in simplifying the structure. These antennas have a drawback in that as the number of sectors increases, the antenna size rapidly increases. Therefore, downsizing the sector antenna has become a major research topic. A promising candidate is utilizing a phased-array type antenna; however, this antenna requires a phase-shifter circuit for beam scanning and generally the feeding circuit for this type of antenna is very complicated. To address these issues, we propose a self-selecting feeding circuit that is controlled by the same control circuit and is operated similarly to the conventional single port n-th throw (SPNT) switch. We fabricated a small cylindrical 12-sector antenna at 19 GHz employing the proposed feeding circuit for verification purposes. Furthermore, this paper clarifies the design method of this feeding circuit where the antenna diameter is 71 mm, and the results clearly show that the gain is more than 12 dBi.

This paper elucidates the most appropriate hybrid automatic-repeat-request (ARQ) scheme, i.e., which can achieve the highest throughput, for high-speed packet transmission in the W-CDMA forward link by comparing the throughput performance of three types of hybrid ARQ schemes: type-I hybrid ARQ with packet combining (PC), type-II hybrid ARQ, and basic type-I hybrid ARQ as a reference. Moreover, from the viewpoint of maximum throughput, the respective optimum roles of ARQ and channel coding in hybrid ARQ are also clarified, such as the optimum coding rate and the packet length related to the interleaving effect. The simulation results reveal that the type-II scheme exhibits the best throughput performance, and the required received signal energy per chip-to-background noise spectral density ratio (Ec/N0) at the throughput efficiency of 0.2/0.4/0.6 is improved by 0.7/0.3/0.1 dB and 3.9/1.8/0.5 dB, respectively, compared to the type-I scheme with and without PC in a 2-path Rayleigh fading channel with the average equal power at the maximum Doppler frequency of 5 Hz and the packet length of 4 slots (= 0.667 4 = 2.667 msec). However, the improvement of the type-II scheme compared to the type-I scheme with PC is small or the achievable throughput is almost identical in the high-received Ec/N0 region. On the other hand, the type-I scheme with PC is much less complex and thus preferable, while maintaining almost the same throughput performance or allowing very minor degradation compared to that with type-II. The results also elucidate that, while the optimum coding rate depends on the required throughput in the basic type-I and type-I with PC schemes, it is around between 3/4 and 8/9 in type-II, resulting in a higher throughput efficiency. In addition, for high-speed packet transmission employing a hybrid ARQ scheme, a shorter retransmission unit size is preferable such as 1 slot, and the fast transmit power control is effective only under conditions such as a low maximum Doppler frequency and a high transmit Ec/N0 region.

EMI coupling paths in an electronic controller are investigated experimentally. Common-mode current measurements on the attached cable are used for diagnosing changes made to the EMI coupling path. Experiments that include shielding various portions of the PCB, and re-routing high-speed traces are conducted to characterize the coupling path. A means of identifying and characterizing EMI coupling paths in functioning hardware, and relating them to design features, is demonstrated.

In this paper, we present a low-power and area-efficient design method of embedded high-speed A/D converters for mixed analog-digital system LSI's. As the A/D converter topology, a 1.5 bit/stage interleaved pipeline A/D converter is employed, because the basic topology covers a wide range of specifications on the conversion frequency and the resolution. The design method determines the minimum DC supply current, the minimum device sizes and the minimum number of channels to meet the precision given by the specification. This paper also points out that the interleaved pipeline structure is very effective for low-power design of high-speed A/D converters whose sampling frequency is over 100 MHz.

Flow control algorithm in high speed networks is a resource-sharing policy implemented in a distributed manner. This paper introduces a novel concept of backlog balancing and demonstrates its application to network flow control and congestion control by presenting a rate-based flow control algorithm for ATM networks. The aim of flow control is to maximize the network utilization for achieving high throughput with tolerable delay for each virtual circuit (VC). In a resource-sharing environment, this objective may also cause network congestion when a cluster of aggressive VC's are contending for the same resource at a particular node. The basic idea of our algorithm is to adjust the service rate of each node along a VC according to backlog discrepancies between neighboring nodes (i.e., to reduce the backlog discrepancy). The handshaking procedure between any two consecutive nodes is carried out by a link-by-link binary feedback protocol. Each node will update its service rate periodically based on a linear projection model of the flow dynamics. The updated service rate per VC at a node indicates its explicit demand of bandwidth, so a service policy implementing dynamic bandwidth allocation is introduced to enforce such demands. Simulation study has validated the concept and its significance in achieving the goal of flow control and yet preventing network congestion at the same time.

The interconnect analysis of on- and off-chips is very important in the design of high-speed signal processing, digital communication, and microwave electronic systems. When the interconnects are characterized by sampled data via electromagnetic analysis, the circuit-level simulation of the network requires rational approximation of the sampled data. Since the frequency band of the sampled data is more than 10 GHz, the rational function must fit into it at many frequency points. The rational function is approximated using the orthogonal least-squares method. With an increase in the number of the fitting data, the least-squares method suffers from a singularity problem. To avoid this, the sampled data are hierarchically approximated in this paper. Moreover, to reduce the computational cost of the circuit-level simulation, the parameter matrix of the interconnects is approximated by a rational matrix with one common denominator polynomial, and the selective orthogonalization procedure is presented.

This paper proposes a new digital beamforming adaptive array antenna (DBFAAA) that is effective in severe multipath environments in which timing and carrier synchronization circuits cannot function ideally resulting in the DBFAAA losing control. The proposed DBFAAA has two stages. In the first, the DBFAAA captures the desired signal and establishes synchronization. In the second, the DBFAAA optimizes the beam pattern of the signal. The proposed configuration employs an eigenvector beam of the maximum eigenvalue in the first stage beam-forming. In addition, a fractionally-spaced-tapped-delay-line (FS-TDL) with real tap weights, which is placed after the beam-former, is applied to achieve timing synchronization. The behavior of the proposed DBFAAA for asynchronous sampling data is investigated and the results indicate that the proposed configuration enables asynchronous sampling at the A/D converter. A prototype of the proposed DBFAAA achieving 38-Mbps real-time data communication is introduced and the transmission performance is shown.

Developments in new frequency bands for wireless communications make a broadband channel for new services possible. Great effort has been made researching and developing broadband wireless communication in the 60-GHz millimeter-wave band since the early 1990s. In this paper, we design an ATM (asynchronous transfer mode)-based indoor millimeter-wave wireless local area network (WLAN) that supports multimedia transmissions and focus on the wireless access topic for implementation of wireless ATM. We propose an integrated multimedia transmission protocol, based on the MAC (medium access control) protocol, called RS-ISMA (reservation-based slotted idle signal multiple access). It supports CBR (constant bit rate), VBR (variable bit rate), ABR (available bit rate) and UBR (unspecified bit rate) transmissions and provides QoS (quality of service)-dependent adaptive retransmissions. An RS-ISMA-based prototype full-duplex indoor high-speed WLAN in the 60-GHz band was developed.

This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulation-based performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware.

The rapid growth of the Internet impacts ATM networks to be furnished IP handling capability. This paper discusses networking issues for IP and ATM integration. First, it considers function allocation at the boundary of an ATM backbone network and the Internet. As the result, the paper explains the necessity of built-in IP handling capability into an ATM switching system, and summarizes functional requirements for the system architecture. According to the discussion above, the authors propose the system architecture of the IP/ATM integration in the ATM switching system. The implementation of the proposed architecture is evaluated, and the wire-speed IP handling capability in the ATM switch is confirmed.

This paper describes a 0.35µm SOI-CMOS gate array using partially-depleted transistors. The gate array adopts the field-shield isolation technique with body-tied structures to suppress floating-body problems such as: (1) kink characteristics in drain currents, (2) low break-down voltage, and (3) frequency-dependent delay time. By optimizing the basic-cell layout and power-line wiring, the SOI-CMOS gate array also allows the use of the cell libraries and the design methodologies compatible with bulk-CMOS gate arrays. An ATM (Asynchronous Transfer Mode) physical-layer processing LSI was fabricated using a 0.35µm SOI-CMOS gate array with 560k raw gates. The LSI operated at 156 Mbps at 2.0 V, while consuming 71% less power than using a typical 0.35µm 3.3 V bulk-CMOS gate array.

The architecture design and test results of simulation facility named millimeter-wave Test Bed has been described. Contrast with a millimeter-wave sounder, the Test Bed proposed in this paper can characterize radio channels, received signals, target reflections and radio link performance at the millimeter-wave band of 60 GHz. For fixible simulation and analysis of the performances of newly designed millimeter-wave systems, major digital signal processing parts like a sophisticate waveform generator and an analyzer, a modulator, a demodulator, an encoder, a decoder, an equalizer in the Test Bed are implemented by a software using SPW. This software based Test Bed can be used as a "deign tool" for the simulation of the millimeter-wave communication systems very flexibly without hardware modification in different specifications. The Test Bed consists of a millimeter-wave transmitter, a receiver of 60 GHz, 1.95 GHz up/down converter as IF module and a digital signal processing module. The I/Q vector modulator and demodulator with a video bandwidth of 37.5 MHz in the Test Bed can simulate or test the application of high data rate communication systems of short distance.

A high-speed dynamic reference single-ended ECL input-interface circuit has been fabricated for advanced ATM switching MCMs. To raise the limit on the number of I/O pins, this circuit operates with a reference signal directly generated from the input signal itself. The reference level is changed dynamically to achieve a larger noise margin for operation. Experimental results show that operation up to 3.4 Gbps with a large level margin can be attained. We deploy this circuit to the input interface LSIs of an 80-Gbps ATM switching MCM.

A high-speed static logic circuit, the 1:8 demultiplexer (DEMUX), fabricated using single-gate CMOS technology (single-gate means the structure consisting of n+ poly-Si gate for both NMOS and PMOS transistors) has been demonstrated. To suppress short-channel effects in PMOS transistors, we only used the low-energy ion implantation (I/I) of BF2 at 10 keV for counterdoping of the channel and that at 5 keV for source/drain (S/D) extension. To control the threshold voltage Vth of PMOS transistors precisely, the channel dopants were implanted after the growth of the gate oxide because of the suppression of the transient-enhanced diffusion (TED) of boron, and the suppression of boron out-diffusion. A tree-type 1:8 DEMUX circuit composed of 0. 134 µm gate CMOS transistors operates at a high speed of 3.1 GHz and consumes a low power of 35.5 mW/GHz at VDD = 2.0 V. In this single-gate CMOS circuit, down to this small gate length, the maximum operating frequency of the DEMUX circuit increases proportionally with an increase of the inverse of the gate length without an increase of power consumption per GHz. At a practical 2.48832 Gb/s operation, the power consumption was 88 mW, and the phase margin between the input clock signal and the input data signal was 260 ps. It is suggested that a circuit composed of a single-gate CMOS transistor with 0.15 µm gate generation can be applicable to high speed ICs.

This paper proposes a novel ultra high-speed file server based on a personal computer (PC) to provide the instantaneous delivery of huge files, like movie files, graphic images and computer programs, over high-speed networks. In order to improve the sustained sequential read speed from arrays of hard drives to host memory in the server, two key techniques are proposed: "multi-stage striping (MSS)" and the "sequential file system (SFS)." An experimental file server based on a general-purpose PC is constructed and its performance is measured. The results show that the server offers ultra high read speeds, up to 105Mbytes/s, with just 8 hard drives.

We have designed rapid single-flux-quantum (RSFQ) adder circuits using two different architectures: one is the conventional architecture employing globally synchronous clocking and the other is the data-driven self-timed (DDST) architecture. It has been pointed out that the timing margin of the RSFQ logic is very sensitive to the circuit parameter variations which are induced by the fabrication process and the device parameter uncertainty. Considering the physical timing in the circuits, we have shown that the DDST architecture is advantageous for realizing RSFQ circuits operating at very high frequencies. We have also calculated the theoretical circuit yield of the DDST adders and shown that a four-bit system operating at 10 GHz is feasible with sufficient operating margin, considering the present 1 kA/cm2 Nb Josephson technology.

The switch LSI described here takes advantage of the special characteristics of fully-depleted CMOS/SIMOX devicesthat is, source/drain capacitances and threshold voltages that are lower than those of conventional bulk CMOS devicesto boost the I/O bit rate. The double-edge triggered MUX/DEMUX which uses a frame synchronization logic, and the active-pull-up I/O provide a 144-pin, 2. 5-Gbps/pin interface on the chip. The 220-kgate rerouting banyan switching network with 110-kbit RAM operates at an internal clock frequency of 312 MHz. The CMOS/SIMOX LSI consumes 8. 4 W when operating with a 2-V power supply, and has four times the throughput of conventional one-chip ATM switch LSIs.

We describe the design of ECL write circuits and a CMOS memory cell in an ECL-CMOS SRAM to achieve ultra-fast cycle time. Factors determining the write cycle are reduced by several novel circuit techniques and by optimizing the design of the write circuits and CMOS memory cell, thereby, enabling ultra-fast cycle time. Key techniques are a bit line overdriving, the use of an overshoot suppressing emitter follower and a WPG with a replica memory cell delayer. The 72-kb ECL-CMOS SRAM macro through which these techniques were implemented was fabricated using 0. 3-µm BiCMOS technology. The RAM macro achieves a short cycle time of 2 ns without sacrificing stable memory cell operation. These techniques thus provide SRAMs with a shorter cycle time in the cache memories of high performance computer systems.

Optimization of InGaAs/InAlAs multiple quantum well structures for high-speed and low-driving modulation, as well as polarization insensitivity and low chirp, was investigated as a function of well thickness and strain magnitude. As a result, very short optical pulses with 4-6 ps was obtained using a low driving-voltage (<2. 0 Vpp) electroabsorption modulator module operating at a 40-GHz large signal modulation. Small chirp operation for low insertion loss (<8 dB from fiber-to-fiber) with prebias was also demonstrated and the product of the pulse width and the spectral width was estimated to be 0. 39 for a 5 ps pulse width that is nearly transform-limited.

This paper proposes a high-speed input and output buffering ATM switch, named Tandem-Crosspoint (TDXP) switch. The TDXP switch consists of multiple crossbar switch planes. These switch planes are connected in tandem at every crosspoint. Even if a cell can not be transmitted to an output port on the first plane, it has a chance to be transmitted on the next plane. Cell transmission is executed on each switch plane in a pipeline manner. Therefore, more than one cell can be transmitted to the same output port within one cell time slot, although the internal line speed of each switch is equal to the input /output line speed. The TDXP switch architecture has several advantages in implementation. First, the TDXP switch does not increase the internal line speed in eliminating Head-Of-Line (HOL) blocking. Second, since the TDXP switch employs a simple cell reading algorithm at the input buffer in order to retain the cell sequence, the TDXP switch does not require to rebuild the cell sequences at output buffers using time stamps, as is required by a parallel switch. These merits make implementing the high-speed ATM switch easy. Numerical results show that the TDXP switch can eliminate the HOL blocking effectively and achieve high throughput both for unicasting and multicasting traffic. This switch architecture is expected to enable the development of high-speed ATM switching systems that can realize over 1 Tb/s throughput in a cost-effective way.