In this paper, we propose an algorithm that enhances the number of pixels for high-speed imaging. High-speed cameras have a principle problem that the number of pixels reduces when the number of frames per second (fps) increases. To enhance the number of pixels, we suppose an optical structure that block-randomly selects some percent of pixels in an image. Then, we need to reconstruct the entire image. For this, a state-of-the-art method takes three-dimensional reconstruction strategy, which requires a heavy computational cost in terms of time. To reduce the cost, the proposed method reconstructs the entire image frame-by-frame using a new cost function exploiting two types of sparsity. One is within each frame and the other is induced from the similarity between adjacent frames. The latter further means not only in the image domain, but also in a sparsifying transformed domain. Since the cost function we define is convex, we can find the optimal solution using a convex optimization technique with small computational cost. We conducted simulations using grayscale image sequences. The results show that the proposed method produces a sequence, mostly the same quality as the state-of-the-art method, with dramatically less computational time.

Break arcs are rotated with the radial magnetic field formed by a magnet embedded in a fixed cathode contact. The break arcs are generated in a 48VDC resistive circuit. The circuit current when the contacts are closed is 10A. The depth of the magnet varies from 1mm to 4mm to change the strength of the radial magnetic field for rotating break arcs. Images of break arcs are taken by two high-speed cameras from two directions and the rotational motion of the break arcs is observed. The rotational period of rotational motion of the break arcs is investigated. The following results are obtained. The break arcs rotate clockwise on the cathode surface seen from anode side. This rotation direction conforms to the direction of the Lorentz force that affects to the break arcs with the radial magnetic field. The rotational period gradually decreases during break operation. When the depth of magnet is larger, the rotational period becomes longer.

High structural perfection, wafer uniformity, and reproducibility are key parameters for high-volume, low cost manufacture of resonant tunnelling diode (RTD) terahertz (THz) devices. Low-cost, rapid, and non-destructive techniques are required for the development of such devices. In this paper, we report photoluminescence (PL) spectroscopy as a non-destructive characterisation technique for high current densityInGaAs/AlAs/InP RTD structures grown by metal-organic vapour phase epitaxy (MOVPE) for THz applications. By using a PL line scanning technique across the edge of the sample, we identify characteristic luminescence from the quantum well (QW) and the undoped/n+ InGaAs layers. By using the Moss-Burstein effect, we are able to measure the free-electron concentration of the emitter/collector and contact layers in the RTD structure. Whilst the n+ InGaAs luminescence provides information on the doping concentration, information on the alloy composition and compositional variation is extracted from the InGaAs buffer layer. The QW luminescence provides information on the average well width and provides a monitor of the structural perfection with regard to interface and alloy disorder.

Copper arc runners are fixed on silver electrical contacts. Break arcs are generated between the contacts in a DC resistive circuit. Circuit current when contacts are closed is 10A. Supply voltage is changed from 200V to 450V. The following results are shown. Cathode spots stay on the cathode surface but anode spots run on the runner when the supply voltage is 250V and over. In cases of the supply voltage is greater than 250V, the break arcs run on the runner when the arcs are successfully extinguished, and stays on the runner in cases of the failure of arc extinction. The arc lengths just before arc extinction with or without the runners are also investigated. The arc lengths are the same with or without the runners for each supply voltage.

This paper presents an analog front-end circuit for a 60-GHz proximity wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224mW Power consumption.

The data rate of VLSI interconnections has been increasing according to the demand for high-speed operation of semiconductors such as CPUs. To realize high performance VLSI systems, high-speed data communication has become an important factor. However, at high-speed data rates, it is difficult to achieve accurate communication without bit errors because of inter-symbol interference (ISI). This paper presents high-speed data communication techniques for VLSI systems using Tomlinson-Harashima Precoding (THP). Since THP can eliminate the ISI with limiting average and peak power of transmitter signaling, THP is suitable for implementing advanced low-voltage VLSI systems. In this paper, 4-PAM (Pulse amplitude modulation) with THP has been employed to achieve high-speed data communication in VLSI systems. Simulation results show that THP can remove the ISI without increasing peak and average power of a transmitter. Moreover, simulation results clarify that multiple-valued data communication is very effective to reduce implementation costs for realizing high-speed serial links.

Smart city services are implemented using various data collected from houses and infrastructure within a city. As the volume and variety of the smart city data becomes huge, individual services have suffered from expensive computation effort and large processing time. In order to reduce the effort and time, this paper proposes a concept of Materialized View as a Service (MVaaS). Using the MVaaS, every application can easily and dynamically construct its own materialized view, in which the raw data is converted and stored in a convenient format with appropriate granularity. Thus, once the view is constructed, the application can quickly access necessary data. In this paper, we design a framework of MVaaS specifically for large-scale house log, managed in a smart-city data platform. In the framework, each application first specifies how the raw data should be filtered, grouped and aggregated. For a given data specification, MVaaS dynamically constructs a MapReduce batch program that converts the raw data into a desired view. The batch is then executed on Hadoop, and the resultant view is stored in HBase. We present case studies using house log in a real home network system. We also conduct an experimental evaluation to compare the response time between cases with and without MVaaS.

Break arcs are generated in a DC48V and 12A resistive circuit. Silver electrical contacts are separated at constant opening speed. The cathode contact surface is irradiated by a blue LED. The center wavelength of the emission of the LED is 470nm. There is no spectral line of the light emitted from the break arcs. Only the images of contact surface are observed by a high-speed camera and an optical band pass filter. Another high-speed camera observes only the images of the break arc. Time evolutions of the cathode surface morphology being eroded by the break arcs and the motion of the break arcs are observed with these cameras, simultaneously. The images of the cathode surface are investigated by the image analysis technique. The results show that the moments when the expanded regions on the cathode surface are formed during the occurrence of the break arcs. In addition, it is shown that the expanded regions are not contacted directly to the cathode roots of the break arcs.

An amplitude shift keying transmitter and receiver chipset with low power consumption using 40nm CMOS technology for wireless communication systems is described, in which a maximum data rate of 10Gbps and power consumption of 98.4mW are obtained with a carrier frequency of 135GHz. A simple circuit and a modulation method to reduce power consumption are selected for the chipsets. To realize multi-gigabit wireless communication, the receiver is designed considering the group delay optimization. In the receiver design, the low-noise amplifier and detector are designed considering the total optimization of the gain and group delay in the millimeter-wave modulated signal region.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

This paper presents a 7-bit 1.5-GS/s time-interleaved (TI) SAR ADC. The scheme achieves better isolation between sub-ADCs thanks to embedding a track-and-hold (T/H) amplifier and reference voltage buffer in each sub-ADC. The proposed dynamic T/H circuit enables high-speed, low-power operation. The prototype is fabricated in a 65-nm CMOS technology. The total active area is 0.14,mm2 and the ADC consumes 36 mW from a 1.2-V supply. The measured results show the peak spurious-free dynamic range (SFDR) and signal-to-noise-and-distortion ratio (SNDR) are 52.4 dB and 39.6 dB, respectively, and an figure of Merit (FoM) of 300 fJ/conv. is achieved.

In this paper, we propose a high-speed full-duplex optical wireless communication system using a single channel imaging receiver for personal area network applications. This receiver is composed of an imaging lens, a small sensitive-area photodiode, and a 2-aixs actuator and it can reject most of the background light. Compared with the previously proposed system with single wide field-of-view (FOV) non-imaging receiver, the coverage area at 12.5 Gb/s is extended by > 20%. Furthermore, since the rough location information of the user is available in our proposed system, instead of searching for the focused light spot over a large area on the focal plane of the lens, only a small possible area needs to be scanned. In addition, by pre-setting a proper comparison threshold when searching for the focused light spot, the time needed for searching can be further reduced. Proof-of-concept experiments have been carried out and the results show that with this partial searching algorithm and pre-set threshold, better performance is achieved.

To clarify the characteristics of high-speed electrostatic discharge (ESD) events, we use two kinds of discharge electrodes: sphere- and cylinder-shape ones. We measure the energy level of ESD waveforms with charging voltages of 0.25, 0.5, and 1.0 kV. We find that the cylindrical electrode yields higher high-speed ESD energies, especially when the charging voltage is high; this indicates that the discharge gap shape is an important factor in ESD events.

Silver electrical contacts are separated at constant speed and break arcs are generated in a DC100 V–450 V/10 A resistive circuit. The transverse magnetic field of a permanent magnet is applied to the break arcs. Dependences of the arc duration, arc dwell time and arc lengthening time on the strength of the magnetic field and supply voltage are investigated. The characteristics of the re-ignition of the break arc are also discussed. Following results are shown. The arc duration D is increased due to the increase of the arc lengthening time tm when the supply voltage E is increased for each magnetic flux density Bx, because the arc dwell time ts is almost constant. The arc duration D is increased due to the increase of both of the arc lengthening time tm and the arc dwell time ts when the magnetic flux density Bx is decreased. The arc lengthening time tended to become long when the re-ignition of the break arc is occurred. The lengthening time tends to become longer when the duration tm1 from the start of the arc lengthening to the start of the re-ignition is increased. Re-ignitions occurred frequently when the magnetic flux density of the transverse magnetic field is increased and the supply voltage is increased.

Break arcs are rotated by the radial magnetic field formed by a magnet embedded in the pipe-shaped cathode. The arcs are generated in switching a DC42 V resistive circuit. The closed contact current varies from 5 A to 21 A. The curvature of the anode surface is varied to study the dependence of the arc length and the positions of the break arcs in the contact gap. The following results are obtained: (i) as current decreases, there is more difference in arc duration among different curvatures; (ii) as current decreases, the arc duration decreases with decrease of the radius of curvature; (iii) in each contact curvature, the anode spots region is located nearer to the center axis than the cathode spots region; (iv) the arc length just before arc extinction is independent of the curvature of the contacts.

Mirrored serpentine microstrip lines are proposed for a parallel high speed digital signaling to reduce the peak far-end crosstalk (FEXT) voltage. Mirrored serpentine microstrip lines consist of two serpentine microstrip lines, each one equal to a conventional normal serpentine microstrip line. However, one serpentine microstrip line of the mirrored serpentine microstrip lines is flipped in the length direction, and thus, two serpentine microstrip lines face each other. Time domain reflectometry measurements show that the peak FEXT voltage of the mirrored serpentine microstrip lines is reduced by 56.4% of that of conventional microstrip lines and 30.0% of that of conventional normal serpentine microstrip lines.

We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed current-mode buck and boost converters and fabricated them using a 0.18-µm high-voltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU time in a boost converter simulation.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

Short-range Multiple-Input-Multiple-Output (SR-MIMO) transmission is an effective technique for achieving high-speed and short-range wireless communication. With this technique, however, the optimum aperture size of array antennas grows when the transmission distance is increased. Thus, antenna miniaturization is an important issue in SR-MIMO. In this paper, we clarify the effectiveness of using dual-polarized planar antennas as a means of miniaturizing SR-MIMO array antennas by measurements and analysis of MIMO transmission characteristics. We found that even in SR-MIMO transmission, the use of dual-polarized transmission enables higher channel capacity. Dual-polarized antennas can reduce by two thirds the array area that is needed to obtain the same channel capacity. For a transmission distance of two wavelengths, the use of a dual-polarized antenna improved the channel capacity by 26 bit/s/Hz while maintaining the same number of transmitters and receivers and the same antenna aperture size. Moreover, dual-polarized SR-MIMO has a further benefit when zero-forcing (ZF) reception without transmit beamforming is adopted, i.e., it effectively simplifies hardware configuration because it can reduce spatial correlation even in narrow element spacing. In this work, we confirmed that the application of dual-polarization to SR-MIMO is an effective way to both increase channel capacity and enhance transceiver simplification.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.