Three miniaturized lumped-element power dividers with a filtering function for use in quadrature mixers are described. Simulation results showed that they can be miniaturized, as compared to conventional ones with open/short stubs, while maintaining the filter characteristics. A fabricated 0.95-GHz 0power divider with a filtering function had a chip size about half that of a conventional lumped-element one. Its insertion loss at 0.950.05 GHz was 4.00.1 dB.

Compact and planar active integrated antenna arrays with a high power multi-stage amplifier were developed with effective heat sink mechanism. By attaching an aluminum plate to the backside of the creased amplifier circuit board, effective cooling can be achieved. The nonlinear behavior of the amplifier agrees well with the simulation based on the Angelov model. The high power amplifier circuit consisted of the three-stage amplifier and operated with an output power of 4 W per each element at 5.8 GHz. The 32-element active integrated antenna array stably operated with the output power of 120 W under the effective heat sink design. With a weight of 4 kg, the weight-to-output power ratio and the volume-to-output power ratio of the antenna array are 33.3 g/W and 54.5 cm3/W, respectively. Wireless power transmission was also successfully demonstrated.

This paper represents a novel second harmonic power combining oscillator using mutually synchronized Gunn diodes embedded on slot line resonators. A both-sided MIC technology is adopted in the oscillator. The oscillator consists of Gunn diodes, slot line resonators and microstrip lines. By embedding Gunn diodes on the slot line resonators, the harmonic RF signal can be generated very easily. The microstrip lines are used for the power combining output circuit. This oscillator has advantages such as easy circuit design, simple circuit configuration and miniaturization of the circuit size. The second harmonic oscillator is designed and fabricated in K-Band. The output power is +5.75 dBm at the design frequency of 19.0 GHz (2f0) with the phase noise of -111.7 dBc/Hz at the offset frequency of 1 MHz. Excellent suppression of the undesired fundamental frequency signal (f0) of -39 dBc is achieved.

A compact circuit model for five-port on-chip transformer balun is presented. Compared to the conventional model, the proposed model is simpler without any accuracy degradation and ensures faster convergence time, which in turn enables flexible RF circuit design optimization. The validity of the proposed model is confirmed through extensive EM simulations and measurements.

In this paper, a new compensation scheme and a corresponding pass element structure for a CMOS low-dropout regulator (LDO) are presented. The proposed approach effectively alleviates the strict stability constraint on the ESR of the output capacitor. Stability of a CMOS LDO with the conventional compensation requires the effective series resistance (ESR) of the output capacitor in a tunnel-like region. With the proposed design approach, an LDO can be stable using an output capacitor without ESR. A 2.5 V/150 mA LDO has been implemented using a 0.5-µm 1P2M CMOS process. The experimental results illustrate that the proposed LDO is stable with an output capacitor of 0.33 µF and no ESR.

This paper will review the development of SiC power devices especially SiC power junction field-effect transistors (JFETs). Rationale and different approaches to the development of SiC power JFETs will be presented, focusing on normally-OFF power JFETs that can provide the highly desired fail-save feature for reliable power switching applications. New results for the first demonstration of SiC Power ICs will be presented and the potential for distributed DC-DC power converters at frequencies higher than 35 MHz will be discussed.

In this paper, we propose a two-microphone noise reduction method to deal with non-stationary interfering noises in multiple-noise-source environments in which the traditional two-microphone algorithms cannot function well. In the proposed algorithm, multiple interfering noise sources are regarded as one virtually integrated noise source in each subband, and the spectrum of the integrated noise is then estimated using its virtual direction of arrival. To do this, we suggest a direction finder for the integrated noise using only two microphones that performs well even in speech active periods. The noise spectrum estimate is further improved by integrating a single-channel noise estimation approach and then subtracted from that of the noisy signal, finally enhancing the desired target signal. The performance of the proposed algorithm is evaluated and compared with the traditional algorithms in various conditions. Experimental results demonstrate that the proposed algorithm outperforms the traditional algorithms in various conditions in terms of objective and subjective speech quality measures.

Impacts of electromagnetic (EM) interference (immunity) on operation of LSI circuits in a QFP-packaged and PCB-mounted environment are studied. EM power injection to a power-supply system leads to malfunction, where the power is translated into voltage bounces through combined on- and off- chip impedances, affecting power supply and ground, as well as signal nodes in a die, seen from on-chip waveform measurements. A lumped power-supply impedance model and the minimum amplitude of voltage bounce induced by EM power for malfunction, both of which can be derived from external measurements to a given packaged LSI, formulate an EM interference model that is helpful in the PCB design toward high immunity. The technique can be generally applied to systems-on-chip applications.

This paper presents a new method for reconstruction of trigonometric polynomials, a specific class of bandlimited signals, from a number of integrated values of input signals. It is applied in signal reconstruction, spectral estimation, system identification, as well as in other important signal processing problems. The proposed method of processing can be used for precise rms measurements of periodic signal (or power and energy) based on the presented signal reconstruction. Based on the value of the integral of the original input (analogue) signal, with a known frequency spectrum but unknown amplitudes and phases, a reconstruction of its basic parameters is done by the means of derived analytical and summarized expressions. Subsequent calculation of all relevant indicators related to the monitoring and processing of ac voltage and current signals is provided in this manner. Computer simulation demonstrating the precision of these algorithms. We investigate the errors related to the signal reconstruction, and provide an error bound around the reconstructed time domain waveform.

Feature transformation in automatic text classification (ATC) can lead to better classification performance. Furthermore dimensionality reduction is important in ATC. Hence, feature transformation and dimensionality reduction are performed to obtain lower computational costs with improved classification performance. However, feature transformation and dimension reduction techniques have been conventionally considered in isolation. In such cases classification performance can be lower than when integrated. Therefore, we propose an integrated feature analysis approach which improves the classification performance at lower dimensionality. Moreover, we propose a multiple feature integration technique which also improves classification effectiveness.

This paper presents the history of superconductor digital circuits starting from several years after the discovery of the Josephson junction in 1962. The first two decades were mainly devoted to developing voltage-state logic, which is similar to semiconductor logic. Research on circuits employing the manipulation of single magnetic flux quanta resulted in a form called RSFQ in the mid-1980s; this is the basis of superconductor logic systems of today. The more difficult problem of random access memory is reviewed. We analyze the present status of the field and outline the work that lies ahead to realize a successful superconductor digital technology.

A cryocooled system with I/O interface circuits, which enables high-speed system operation of superconductive single-flux-quantum (SFQ) circuits at over 40 GHz, and the demonstration of a 47-Gbps SFQ 22 switch system are presented. The cryocooled system has 32 I/Os and cools an SFQ multi-chip module (MCM) to 4 K with a two-stage 1-W Gifford-McMahon cryocooler. An SFQ 4:1 multiplexer (MUX) and an SFQ 1:4 demultiplexer (DEMUX) have been designed to interface the speed gap between the I/O (~10 Gbps/ch) and SFQ circuits (>40 GHz). An SFQ 22 switch chip, in which the MUX/DEMUX and an SFQ 22 switch are integrated, and an 8-channel superconductive voltage driver (SVD) chip have been designed with an advanced cell library for a junction critical current density of 10 kA/cm2. An SFQ 22 switch MCM has been made by flip-chip bonding the switch chip and SVD chip on a superconductive MCM carrier with φ 50-µm InSn solder bumps. An SFQ 22 switch system, which is the switch MCM packaged in the cryocooled system, has been demonstrated up to a port speed of 47 Gbps for the first time.

This paper reviews recent world-wide progress in silicon-based photonics-and-optoelectronics in order to provide a context for the papers in this special section of the IEICE Transactions. The impact of present and potential applications is discussed.

We propose and demonstrate a simple one-bus two-ring configuration where the two rings are mutually coupled that has advantages over the one-ring structure. Unlike a one cavity system, it can exhibit near critically-coupled transmission with a broader range of loss. It can also significantly enhance the cavity finesse by simply making the second ring twice the size of the bus-coupled one, with the enhancement proportional to the intensity buildup in the second ring.

A compact arrayed-waveguide grating with small-bend waveguides incorporating air trenches and high mesa structures has been proposed. An 8-channel, 100-GHz-spacing silica arrayed-waveguide grating was fabricated, and its size was reduced dramatically to 1/4 of that of a conventional device.

We propose a new label recognition system for photonic label routing network. Binary-coded labels in binary phase-shift-keying format are considered. The system consists of an optical waveguide circuit with tree-structure passive asymmetric X-junctions and time gates. The system uses self-routing propagation of an identifying bit by performing interference with address bits. The identifying bit is placed in advance of the address bits in the label. The identifying bit pulse is routed to the destination output port corresponding to the code of the address. The operation principle is described. It is shown that all the binary number codes can be recognized with this system. We discuss the feasibility of the system by evaluating its crosstalk. To reduce the crosstalk, an improved scheme is also presented. The label recognition operation with the optical waveguide device is verified by numerical simulation using the finite-difference beam propagation method.

Closed-form expressions for a crosstalk noise amplitude and worst-case delay in capacitively coupled two-line and three-line systems are derived assuming bus lines and other signal lines in a VLSI. Two modes are studied; a case that adjacent lines are driven from the same direction, and the other case that adjacent lines are driven from the opposite direction. Beside, a junction capacitance of a driver MOSFET is considered. The closed-form expressions are useful for circuit designers in an early stage of a VLSI design to give insight to interconnection problems. The expressions are extensively compared and fitted to SPICE simulations. The relative and absolute errors in the crosstalk noise amplitude are within 63.8% and 0.098 E (where E is a supply voltage), respectively. The relative error in the worst-case delay is less than 8.1%.

A single-chip ubiquitous sensor network (USN) system-on-a-chip (SoC) for small program memory size and low power has been proposed and integrated in a 0.18-µm CMOS technology. Proposed single-chip USN SoC is mainly consists of radio for 868/915 MHz, analog building block, complete digital baseband physical layer (PHY) and media access control (MAC) functions. The transceiver's analog building block includes a low-noise amplifier, mixer, channel filter, receiver signal-strength indication, frequency synthesizer, voltage-controlled oscillator, and power amplifier. In addition, digital building block consists of differential binary phase-shift keying (DPSK) modulation, demodulation, carrier frequency offset compensation, auto-gain control, embedded 8-bit microcontroller, and digital MAC function. Digital MAC function supports 128 bit advanced encryption standard (AES), cyclic redundancy check (CRC), inter-symbol timing check, MAC frame control, and automatic retransmission. These digital MAC functions reduce the processing power requirements of embedded microcontroller and program memory size by up to 56%. The cascaded noise figure and sensitivity of the overall receiver are 9.5 dB and -99 dBm, respectively. The overall transmitter achieves less than 6.3% error vector magnitude (EVM). The current consumption is 14 mA for reception mode and 16 mA for transmission mode.

We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation (PDM) with noisy neural elements, with the aim of developing a possible ultralow-power one-bit analog-to-digital converter. The static and dynamic noises given to the proposed circuits were obtained from device mismatches of current sources (transistors) and externally applied random spike currents, respectively. Through circuit simulations we confirmed that the circuit exhibited noise-shaping properties, and signal-to-noise ratio (SNR) of the network was improved by 7.9 dB compared with that of the uncoupled network as a result of noise shaping.

The trend of microwave circuits has been toward highly integrated systems. Most design tools for designing microwave circuits mounted the linear or the nonlinear devices adopt the fundamental circuit theory using the S matrix on the frequency domain. The harmonic balance method is also used to correspond to the nonlinear circuit. Therefore, the effect of the electromagnetic field, for example, a mutual coupling between sub-circuits through the space is almost disregarded. To calculate these circuits included its surrounding electromagnetic field, the finite difference time domain method combined with the equivalent circuit simulation had been presented as the lumped element FDTD (LE-FDTD) method. In general, even if an analytical target is a linear circuit, the FDTD method requires very long analytical time. In this paper, we propose an efficient LE-FDTD method to reduce the analytical time. We investigate its efficiency to compare with the conventional LE-FDTD method or measurements, consequently, it is confirmed that the proposal method requires only at analytical time of 1/10 compared with the conventional method. We also show that the proposal method is able to analyze characteristics of the active integrated antenna (AIA) which are practicably impossible to analyze by using the conventional method.