The software development process is front-loaded when formal specification is deployed and as a consequence more problems are identified and solved at an earlier point of time. This places extra importance on the quality and efficiency of the different formal specification tasks. We use the term “exploratory modeling” to denote the modeling that is conducted during the early stages of software development before the requirements are clearly understood. We believe tools that support not only rigorous but also flexible construction of the specification at the same time are helpful in such exploratory modeling phases. This paper presents a web-based IDE named VDMPad to demonstrate the concept of exploratory modeling. VDMPad has been evaluated by experienced professional VDM engineers from industry. The positive evaluation resulting from such industrial users are presented. It is believed that flexible and rigorous tools for exploratory modeling will help to improve the productivity of the industrial software developments by making the formal specification phase more efficient.

In general, tunnel diodes exhibit various types of oscillation mode: the sinusoidal mode or the nonsinusoidal mode which is known as the relaxation oscillation (RO) mode. We derive a condition for generating the RO in resonant tunneling diodes (RTDs) with essential components for equivalent circuit model. A conditional equation to obtain sufficient nonlinearity towards the robust RO is clarified. Moreover, its condition also can be applied in case of a bow-tie antenna integrated RTD, thus a design policy to utilize the RO region for the antenna integrated RTD is established by numerical evaluations of time-domain large-signal nonlinear analysis towards a terahertz transmitter for broadband wireless communications.

An output voltage-current equation of charge pump DC-DC voltage multiplier using diodes is provided to cover wide clock frequency and output current ranges for designing energy harvester operating at a near-threshold voltage or in sub-threshold region. Equivalent circuits in slow and fast switching limits are extracted. The effective threshold voltage of the diode in slow switching limit is also derived as a function of electrical characteristics of the diodes, such as the saturation current and voltage slope parameter, and design parameters such as the number of stages, capacitance per stage, parasitic capacitance at the top plate of the main boosting capacitor, and the clock frequency. The model is verified compared with SPICE simulation.

Montgomery modular multiplication is one of the most efficient algorithms for modular multiplication of large integers. On resource-constraint embedded processors, memory-access operations play an important role as arithmetic operations in the modular multiplication. To improve the efficiency of Montgomery modular multiplication on embedded processors, this paper concentrates on reducing the memory-access operations through adding a few working registers. We first revisit previous popular Montgomery modular multiplication algorithms, and then present improved algorithms for Montgomery modular multiplication and squaring for arbitrary prime fields. The algorithms adopt the general ideas of hybrid multiplication algorithm proposed by Gura and lazy doubling algorithm proposed by Lee. By careful optimization and redesign, we propose novel implementations for Montgomery multiplication and squaring called coarsely integrated product and operand hybrid scanning algorithm (CIPOHS) and coarsely integrated lazy doubling algorithm (CILD). Then, we implement the algorithms on general MIPS64 processor and OCTEON CN6645 processor equipped with specific multiply-add instructions. Experiments show that CIPOHS and CILD offer the best performance both on the general MIPS64 and OCTEON CN6645 processors. But the proposed algorithms have obvious advantages for the processors with specific multiply-add instructions such as OCTEON CN6645. When the modulus is 2048 bits, the CIPOHS and CILD outperform the CIOS algorithm by a factor of 47% and 58%, respectively.

A high-image-rejection wireless receiver with an N-phase active RC complex filter is proposed and analyzed. Signal analysis shows that the double-conversion receiver with (N+N2) mixers corrects the gain and phase mismatches of the adjacent image. Monte Carlo simulations evaluate the relation between image-rejection performances and the dispersions of device parameters for the double-conversion wireless receiver. The Monte Carlo simulations show that the image rejection ratio of the adjacent image depends almost only on R and C mismatches in the complex filter.

Frequencies around 300GHz offer extremely broad atmospheric transmission window with relatively low losses of up to 10dB/km and can be regarded as the ultimate platform for ultrahigh-speed wireless communications with near-fiber-optic data rates. This paper reviews technical challenges and recent advances in integrated circuits targeted at communications using these and nearby “terahertz (THz)” frequencies. Possible new applications of THz wireless links that are hard to realize by other means are also discussed.

We have derived the physics-based equivalent circuit model of a semiconductor-integrated bow-tie antenna (BTA) for expressing its impedance and radiation characteristics as a terahertz transmitter. The equivalent circuit branches and components, consisting of 16 RLC parameters are determined based on electromagnetic simulations. All the values of the circuit elements are identified using the particle swarm optimization (PSO) that is one of the modern multi-purpose optimization methods. Moreover, each element value can also be explained by the structure of the semiconductor-integrated BTA, the device size, and the material parameters.

In satellite/terrestrial integrated mobile communication systems (STICSs), a user terminal directly connects both terrestrial and satellite base stations. STICS enables expansion of service areas and provides a robust communication service for large disasters. However, the cell radius of the satellite system is large (approximately 100km), and thus a capacity enhancement of the satellite subsystem for accommodating many users is needed. Therefore, in this paper, we propose an application of two methods — multiple-input multiple-output (MIMO) transmission using multi-satellites and non-orthogonal multiple access (NOMA) for STICS — to realize the performance improvement in terms of system capacity and user fairness. Through numerical simulations, we show that system capacity and user fairness are increased by the proposed scheme that applies the two methods.

A 50-Gb/s optical transmitter, consisting of a 25-Gb/s-class lens-integrated DFB-LD (with -3-dB bandwidth of 20GHz) and a LD-driver chip based on 0.18-µm SiGe BiCMOS technology for inter and intra-rack transmissions, was developed and tested. The DFB-LD and LD driver chip are flip-chip mounted on an alumina ceramic package. To suppress inter-symbol interference due to a shortage of the DFB-LD bandwidth and signal reflection between the DFB-LD and the package, the LD driver includes a two-tap pre-emphasis circuit and a high-speed termination circuit. Operating at a data rate of 50Gb/s, the optical transmitter enhances LD bandwidth and demonstrated an eye opening with jitter margin of 0.23UI. Power efficiency of the optical transmitter at a data rate of 50Gb/s is 16.2mW/Gb/s.

In this paper, a novel multilayer substrate integrated waveguide (SIW) four-way out-of-phase power divider is proposed. It is realized by 3D mode coupling, on multilayer substrates. The structure consists of vertical Y-junction, lateral T-junction of SIW and lateral Y-junction of half-mode SIW. The advantages of the proposed structure are its low cost and ease of fabrication. Also, it can be integrated easily with other planar circuits such as microstrip circuits. An experimental circuit is designed and fabricated using the traditional printed circuit board technology. The simulated and measured results show that the return loss of the input port is above 15 dB over 8 to 11.8 GHz and transmissions are about -7.6±1.6 dB in the passband. It is expected that the proposed the proposed power divider will play an important role in the future integration of compact multilayer SIW circuits and systems.

A compact millimeter-wave three-pole dual-band bandpass filter (BPF) by using substrate-integrated waveguide (SIW) dual-mode cavities is developed in this paper. The proposed filter consists of three SIW dual-mode cavities, in which the TE201 and TE102 modes are used to form two passbands. The center frequencies of the two passbands can be readily changed by varying the lengths and/or widths of the SIW cavities. Meanwhile three transmission zeros are produced with appropriate design of the input and output of the SIW cavities, which increase significantly the isolation between the two passbands and their roll-off rate of attenuations. The dual-band BPF filter is designed, fabricated and measured. The measured center frequencies of the two passbands are 26.75GHz and 31.55GHz, respectively. The 3dB-passbands are 26.35-27.15GHz (3%) and 31.29-31.81GHz (1.6%), respectively, with maximum insertion loss of 2.64dB and 4.2dB, respectively, and return loss larger than 12dB in both passbands. A good agreement between the simulated and measured filter characteristics is obtained.

We have studied ultra-low-power superconductor circuits using adiabatic quantum flux parametron (AQFP) logic. Latches, which store logic data in logic circuits, are indispensable logic elements in the realization of AQFP computing systems. Among them, feedback latches, which hold data by using a feedback loop, have advantages in terms of their wide operation margins and high stability. Their drawbacks are their large junction counts and long latency. In this paper, we propose a majority gate-based feedback latch for AQFP logic with a reduced number of junctions. We designed and fabricated the proposed AQFP latches using a standard National Institute of Advanced Industrial Science and Technology (AIST) process. The measurement results showed that the feedback latches operate with wide operation margins that are comparable with circuit simulation results.

A rapid single-flux-quantum (RSFQ) 4-bit bit-slice multiplier is proposed. A new systolic-like multiplication algorithm suitable for RSFQ implementation is developed. The multiplier is designed using the cell library for AIST 10-kA/cm2 1.0-µm fabrication technology (ADP2). Concurrent flow clocking is used to design a fully pipelined RSFQ logic design. A 4n×4n-bit multiplier consists of 2n+17 stages. For verifying the algorithm and the logic design, a physical layout of the 8×8-bit multiplier has been designed with target operating frequency of 50GHz and simulated. It consists of 21 stages and 11,488 Josephson junctions. The simulation results show correct operation up to 62.5GHz.

Safety is the foremost requirement of avionics systems on aircraft. So far, avionics systems have evolved into an integrated system, i.e., integrated avionics system, and the derivative functions occur when the avionics systems are upgraded. However, the traditional safety analysis method is insufficient to be utilized in upgraded avionics systems due to these derivative functions. In this letter, a safety evaluation scheme is proposed to quantitatively evaluate the safety of the upgraded avionics systems. All the functions including the derivative functions can be traced and covered. Meanwhile, a set of safety issues based on different views is established to evaluate the safety capability from three layers, i.e., the mission layer, function layer and resource layer. The proposed scheme can be considered as an efficient scheme in the safety validation and verification in the upgraded avionics systems.

Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.

Change-aware development environments can automatically record fine-grained code changes on a program and allow programmers to replay the recorded changes in chronological order. However, since they do not always need to replay all the code changes to investigate how a particular entity of the program has been changed, they often eliminate several code changes of no interest by manually skipping them in replaying. This skipping action is an obstacle that makes many programmers hesitate when they use existing replaying tools. This paper proposes a slicing mechanism that automatically removes manually skipped code changes from the whole history of past code changes and extracts only those necessary to build a particular class member of a Java program. In this mechanism, fine-grained code changes are represented by edit operations recorded on the source code of a program and dependencies among edit operations are formalized. The paper also presents a running tool that slices the operation history and replays its resulting slices. With this tool, programmers can avoid replaying nonessential edit operations for the construction of class members that they want to understand. Experimental results show that the tool offered improvements over conventional replaying tools with respect to the reduction of the number of edit operations needed to be examined and over history filtering tools with respect to the accuracy of edit operations to be replayed.

We review recent progress in integrated photonics devices and their applications for datacom. In addition to current technology used in 100-Gigabit Ethernet (100GbE) with a compact form-factor of the transceiver, the next generation of technology for 400GbE seeks a larger number of wavelengths with a more sophisticated modulation format and higher bit rate per wavelength. For wavelength scalability and functionality, planar lightwave circuits (PLCs), such as arrayed waveguide gratings (AWGs), will be important, as well higher-order-modulation to ramp up the total bit rate per wavelength. We introduce integration technology for a 100GbE optical sub-assembly that has a 4λ x 25-Gb/s non-return-to-zero (NRZ) modulation format. For beyond 100GbE, we also discuss applications of 100GbE sub-assemblies that provide 400-Gb/s throughput with 16λ x 25-Gb/s NRZ and bidirectional 8λ x 50-Gb/s four-level pulse amplitude modulation (PAM4) using PLC cyclic AWGs.

This paper presents two new types of markers of M-CubITS (M-sequence Multimodal Markers for ITS; M-Cubed for ITS) that is a ground-based positioning system, in order to advance the WYSIWYAS (What You See Is What You Are Suggested) navigation environments providing intuitive guidance. One of the new markers uses warning blocks of textured paving blocks that are often at important points as for pedestrian navigation, for example, the top and bottom of stairs, branch points, and so on. The other uses interlocking blocks that are often at wide spaces, e.g., pavements of plazas, parks, sidewalks and so on. Furthermore, we construct the integrated pedestrian navigation system equipped with the automatic marker-type identification function of the three types of markers (the warning blocks, the interlocking blocks, and the conventional marker using guidance blocks of textured paving blocks) in order to enhance the spatial availability of the whole M-CubITS and the navigation system. Consequently, we show the possibility to advance the WYSIWYAS navigation environments through the performance evaluation and the operation confirmation of the integrated system.

We propose the concept of an integrated coherent photonic wireless transmitter based on the simultaneous injection locking of two monolithically integrated distributed feedback (DFB) laser diodes (LDs) using an optical frequency comb (OFC). We characterize the basic operation of the transmitter and demonstrate that two injection-locked integrated DFB LDs are sufficiently stable to generate the carrier signal using a uni-traveling-carrier photodiode (UTC-PD) for a real-time error-free (bit error rate: BER < 10-11) coherent transmission with a data rate of 10 Gbit/s at a carrier frequency of 97 GHz. In the coherent wireless transmission, we compare the BER characteristics of the injection-locked transmitter with that of an actively phase-stabilized transmitter and show that the power penalty of 8-dB for the injection-locked transmitter is due to the RF spurious components, which can be reduced by integrating the OFC generator (OFCG) and LDs on the same chip. Our results suggest that the integration of the OFCG, DFB LDs, modulators, semiconductor optical amplifiers, and UTC-PD on the same chip is a promising strategy to develop a practical real-time ultrafast coherent millimeter/terahertz wave wireless transmitter.

We have developed a capacitance sensor of frequency modulation for integrated touchpanels using amorphous In-Sn-Zn-O (α-ITZO) thin-film transistors (TFTs). This capacitance sensor consists of a ring oscillator, whose one stage is replaced by a reset transistor, sensing transistor, and sensing electrode. The sensing electrode is prepared as one terminal to form a sensing capacitor when the other terminal is added by a finger. The ring oscillator consists of pseudo CMOS inverters. We confirm that the oscillation frequency changes when the other terminal is added. This result suggests that this capacitance sensor can be applied to integrated touchpanels on flatpanel displays.