A compact Ku-band 5-bit monolithic microwave integrated circuit (MMIC) phase shifter has been demonstrated. The total gate width of switching FETs and the total inductance of spiral inductors are proposed as the figures of merit for compactness. The phase shifter uses the T-type and PI-type high-pass filter (HPF)/band-pass filter (BPF) circuits in which FET "off"-state capacitances are incorporated as the filter elements. According to the figures of merit, the T-type is selected for 90-degree phase shift circuit and the PI-type is selected for the 45-degree phase shift circuit. The fabricated 5-bit phase shifter performs average insertion loss of 5.6 dB and RMS phase shift error of 3.77 degrees with die size of 1.65 mm 0.76 mm (1.25 mm2) in Ku-band.

A C-Ku band 5-bit MMIC phase shifter using optimized reflective series/parallel LC circuits is presented. The proposed circuit has frequency independent characteristics in the case of 180 phase shift, ideally. Also, an ultra-broad-band circuit design theory for the 180 optimized reflective circuit has derived, which gives optimum characteristics compromising between loss and phase shift error. The fabricated 5-bit MMIC phase shifter with SPDT switch has successfully demonstrated a typical insertion loss of 9.4 dB 1.4 dB, and a maximum RMS phase shift error of 7 over the 6 to 18 GHz band. The measured results validate the proposed design theory of the phase shifter.

We developed a process to fabricate optical functions such as, lens, prism, or diffuser directly on to a glass substrate. Processes include precision mastering by diamond cutting, and multi-layer photopolymer (2P) molding process to realize flat surface and integration of multiple functions with a good alignment within few micrometers.

In a fixed-channel-allocation (FCA) cellular network, a fixed number of channels are assigned to each cell. However, under this scheme, the channel usage may not be efficient because of the variability in the offered traffic. Different approaches such as channel borrowing (CB) and dynamic channel allocation (DCA) have been proposed to accommodate variable traffic. Our work expands on the CB scheme and proposes a new channel-allocation scheme--called mobile-assisted connection-admission (MACA) algorithm--to achieve load balancing in a cellular network, so as to assure network communication. In this scheme, some special channels are used to directly connect mobile units from different cells; thus, a mobile unit, which is unable to connect to its own base station because it is in a heavily-loaded "hot" cell, may be able to get connected to its neighboring lightly-loaded cold cell's base station through a two-hop link. Research results show that MACA can greatly improve the performance of a cellular network by reducing blocking probabilities.

This paper first presents an active integrated antenna configuration designed for broadband mobile wireless access systems using the 25-GHz band. This active integrated antenna comprises a microstrip antenna array and RF front-end circuits adopting spatial power combining schemes for reduced power consumption of the power amplifiers. Furthermore, the antenna and RF circuits are integrated into each side of a thick copper backing plate and both are connected through microstrip line /slot transitions. The developed active integrated antenna achieves the output power of 14.6 dBm and a noise figure of less than 5 dB. The wireless system using the developed active integrated antenna achieves a 6-dB improvement in the packet error rate compared to that using a passive antenna with the same array design as the active integrated antenna. Furthermore, we obtained the first license of the active integrated antenna for commercial use in high-speed wireless communication systems in Japan.

The first implementations of X-band AlGaN/GaN HEMT single-ended frequency doublers are presented in this paper. Two types of fundamental frequency signal reflector schemes have been demonstrated for the frequency doubler application. Open-circuited quarter-wavelength microstrip line at the fundamental frequency is utilized for the reflector in a conventional way. In the other architecture a printed antenna is employed as a radiator as well as a novel fundamental frequency reflector. A microstrip rectangular patch antenna operating at the second harmonic frequency of the doubler was designed and integrated with AlGaN/GaN HEMT based on active integrated antenna design concept. Using AlGaN/GaN HEMT with 1 mm gate periphery, two 4 to 8 GHz frequency doublers were designed by the described design methodologies, fabricated, and tested. For the conventional frequency doubler, a conversion gain of 0.6 dB and with an output power of 15 dBm was observed. A conversion gain of 5 dB and an output power of 25 dBm with embedded antenna gain were achieved at a drain voltage of 12 V for the doubler integrated with the patch antenna.

The low phase noise, low supply voltage 1.3 GHz CMOS VCO has been realized by 0.25 µm standard CMOS technology without any trimming and any tuning. The phase noise characteristics of -109 dBc/Hz and -123 dBc/Hz at 100 kHz offset and 500 kHz offset were achieved from carrier, respectively, with 1.3 GHz oscillation frequency at 1.4 V supply voltage. The performance of 1.4 V supply voltage phase noise was superior to that of 2.0 V supply voltage phase noise due to low output impedance current source. The tuning ranges of 13.3%, 16.6%, and 20.1% for 1.4 V, 1.8 V, and 2.0 V supply voltage were achieved, respectively. The amplifier consisted of one pair of PMOS differential stage with large gate length NMOS current source to realize low supply voltage operation and to avoid flicker noise contribution for phase noise. The on-chip spiral inductor consisted of three terminals arranged in a special shape to obtain high Q and small chip area. The power dissipation of this VCO was 22.4 mW without buffer amplifier.

A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOSFET (FG-MOSFET) is proposed. First, the grounded VCLVR realization is discussed. The proposed circuit consists of only an ordinary MOSFET and an FG-MOSFET. The advantages of the proposed VCLVR are low-power and wide-input range and also the power consumption of the proposed VCLVR is the same as an ordinary passive resistor. The performance of the proposed circuits are confirmed by HSPICE simulations with a standard 0.6 µm CMOS process parameters. Simulations of the proposed VCLVR demonstrate a resistance value of 40 kΩ to 338 kΩ and an input range of 4.34 V within THD of less than 1.1%. Next, we proposed a new floating node linear variable resistor using the proposed VCLVR. The performance of the circuit is also evaluated through HSPICE.

In the past, enhancement techniques for the end-to-end quality of a networked application were studied by looking at each individual layer. Examples of such techniques include the error resilience/concealment methods in the application layer, the FEC/ARQ in the transport layer, and the Quality of Service (QoS) techniques in the network layers. However, an integrated approach that would look across all related layers had yet to be investigated. This paper proposes an approach that combines priority-aware video packetization, adaptively used layered FEC, and QoS controlled networks such as IntServ and DiffServ in order to provide an efficient end-to-end quality in layered streaming video. The combination is more efficient in terms of a simple network price mechanism, that is, in getting the best end-to-end quality under a given total cost constraint. Our proposed approach in DiffServ with video packet (VP) data-splitting and layered FEC guarantees minimal service quality in a scalable and cost effective manner without introducing resource reservation. For video, we also propose performance metrics such as corrupted/frozen frame ratio (CFR, FFR). These provide objective metrics like PSNR as well as a measurement for subjective perceptions. Our approach, which combines related layers such as video coding, transport, and network, has yielded results that have proven to be more cost-effective and practical than the supporting network QoS.

This paper describes fully integrated active guard band filters for suppressing the substrate coupling noise and their noise suppression effect measured by test chip experiments. The noise cancellation circuit of the active guard band filters simply consists of an inverter and a source follower. The substrate noise suppression effect was measured by using a test chip fabricated in a 0.18 µm CMOS triple-well process for system-on-a-chip. The noise with the filter was less than 5% of that without the filter and the noise suppression effect was observed from 1 MHz to 200 MHz by the statistical measurement of the voltage comparator. The noise suppression effect was also observed for actual digital switching noise produced by digital inverters. Configuration of the active guard band filter was investigated by simulation and it is shown that high and uniform noise suppression effect is achieved by placing the guard bands in the L-shape around the target triple-well area on the p-substrate.

A new distributed medium access control (MAC) protocol--Soft Reservation Multiple Access with Priority Assignment (SRMA/PA) protocol--is introduced for supporting the integrated services of real-time and non-real-time applications in mobile ad-hoc networks. The SRMA/PA protocol allows the distributed nodes to contend for and reserve time slots with RTS/CTS-like "collision-avoidance" handshake and "soft reservation" mechanism augmented with distributed and dynamic access priority control. The SRMA/PA protocol realizes distributed scheduling for guaranteeing QoS requirements of integrated services and maximizes statistical multiplexing gain. We have demonstrated by simulation studies that the multiplexing gain can be improved significantly without unduly compromising on system complexity. Moreover, we have shown that the proposed back-off mechanism designed for delay-constrained services is useful for further improving utilization of the channel.

This paper presents a fuzzy control-based intelligent medium access controller (FiMAC), which optimizes random access control between heterogeneous traffic aiming at more efficient voice/data integrated services in dynamic reservation TDMA-based broadband radio access networks. In order to achieve the design objective, viz. a differentiated quality-of-service (QoS) guarantee for individual service plus maximal system resource utilization, the FiMAC intelligently and independently controls the random access parameters such as the lengths of random access regions dedicated to respective service traffic and the corresponding permission probabilities, frame-by-frame basis. In addition, we have adopted a mobile-assisted random access mechanism where the voice terminal readjusts a global permission probability from the FiMAC, to handle the 'fair access' issue resulting from distributed queueing problems inherent in the access network. Our extensive simulation results indicate that the FiMAC is well coordinated with a mobile-assisted mechanism such that significant improvements are achieved in terms of voice capacity, delay, and fairness over most of the existing MAC schemes for the integrated services.

This paper presents a second-generation CMOS current conveyor (CCII) consisting of a rail-to-rail complementary n- and p-channel differential input stage for the voltage input, a class AB push-pull stage for the current input, and current mirrors for the current outputs. The CCII was implemented using a double-poly triple-metal 0.6 µm n-well CMOS process, to confirm its operation experimentally. A prototype chip achieves a rail-to-rail swing 2.3 V under 2.5 V power supplies and shows the exact voltage and current following performances up to 100 MHz. Because of its high performances, the CCII proposed herein is quite useful for a building block of current-mode circuits.

Active integrated antennas are a maturing topic. Many novel configurations have been described and system designers are how investigating how the advantages of compactness and increased functionality can be exploited in applications. In this paper, the various types of integrated antennas are discussed together with possible ways of exploiting the technology. New configurations of direct conversion integrated antennas are then described in detail, which illustrate some of the possibilities inherent in the technology.

An LCD Driver IC includes more than 300 buffer amplifiers on a single chip. The phase compensation capacitors (on-chip Miller capacitors) for the amplifiers are more than 1000 pF and occupy a large chip area. This paper describes a two-gain-stage amplifier in which an on-chip Miller capacitor is not used for phase compensation in an LCD Driver IC. In the proposed amplifier, phase compensation is achieved only by a newly introduced zero, which is formed by the load capacitance and a phase compensation resistor connected between the output of the amplifier and the capacitive load. Designs of the phase compensation resistor and the amplifier before compensation are discussed, considering a typical load capacitance range. The test chip was fabricated. The newly introduced zero successfully stabilized the amplifier. The chip area for the amplifier was reduced by 30-40%, compared with our previously reported one. The current consumption of the amplifier was only 5 µA. The experimental results of the fabricated test chip support that the proposed amplifier is suitable to an LCD driver IC with a smaller chip area.

A 6 GHz integrated VCO using SiGe BiCMOS process has been studied. The integrated inductors were realized by third metal with 3 µm thickness aluminum and its Q=20 at 6 GHz. The amplifier consisted of bipolar transistor. Tuning range was 38% with 0 V to 3 V tuning voltage. Phase noise of -100 dBc/Hz was obtained at 1 MHz offset from carrier frequency. The current consumption of VCO was 4.9 mA at 3 V power supply.

This letter proposes a packet length-based group-wise transmission (LGT) rate scheduling scheme for non-real time data service for the uplink of direct sequence code division multiple access (DS/CDMA) system using the burst switching scheme to support the integrated voice/data service. The LGT scheme optimally determines two different rate groups and their optimal data rates so as to minimize the average packet transmission delay. It has shown that the packet transmission delay performance can be significantly improved over the conventional single-rate packet transmission scheme for integrated voice/data service. Furthermore, a main feature of the proposed scheme is simplicity in its implementation.

Fully integrated VCO using the "turbo-charger" technique to improve phase noise characteristics is presented. The phase noise degradation of relatively lower oscillation frequency in tuning range was caused by oscillation amplitude lowering due to large total capacitance. On the other hand, the phase noise degradation of relatively higher frequency in tuning range was caused by excess current noise. A new "turbo-charger" circuit increased operation current to obtain sufficient transconductance of amplifier when oscillation frequency was lower to improve phase noise characteristics. The phase noise of VCO employing this technique was extremely low and stable, below -140-dBc/Hz at 3-MHz offset from oscillation frequency, in wide oscillation frequency range, approximately 200-MHz for 1200-MHz oscillation. This VCO was operated with 5.8-7.4-mA current consumption at 3-V supply voltage. The manufacturing process was 0.6-µm SiGe BiCMOS.

The transfer characteristic of an integrator is affected by excess-phase shift caused by the parasitic capacitance. The phase compensation is obtained by introducing zeros to generate phase lead. This paper proposes a phase compensation technique for the differential signal input integrator. The proposed technique is employing feedforward signal current source. The fifth-order leapfrog Chebyshev low-pass filter with 0.5 dB passband ripple is designed using the integrator with the proposed phase compensation. Further, an autotuning phase compensation system using the proposed technique is realized by applying a PLL system. The effectiveness of the proposed technique is confirmed by PSPICE simulation. The simulation results of the integrator with the proposed phase compensation shows that excess-phase cancellation is obtained at various unity gain frequencies. The accurate filter characteristic of the fifth-order leapfrog filter is obtained by using the autotuning phase compensation system. The passband of the filter is improved over wide range of frequencies. The proposed technique is suitable for low voltage application.