Impulsive noise interference is a significant problem for the Integrated Services Digital Broadcasting for Terrestrial (ISDB-T) receivers due to its effect on the orthogonal frequency division multiplexing (OFDM) signal. In this paper, an adaptive scheme to suppress the effect of impulsive noise is proposed. The impact of impulsive noise can be detected by using the guard band in the frequency domain; furthermore the position information of the impulsive noise, including burst duration, instantaneous power and arrived time, can be estimated as well. Then a time-domain window function with adaptive parameters, which are decided in terms of the estimated information of the impulsive noise and the carrier-to-noise ratio (CNR), is employed to suppress the impulsive interference. Simulation results confirm the validity of the proposed scheme, which improved the bit error rate (BER) performance for the ISDB-T receivers in both AWGN channel and Rayleigh fading channel.

This paper presents a 100–120-GHz pulse transmitter chip with a 5424 on-chip loop antenna array for the purpose of beam-formability in portable millimeter-wave (mm-wave) active imaging applications. We present a new idea for silicon-based mm-wave pulse beam-forming by using voltage-varied CMOS inverter chain. This 4-mm4-mm transmitter chip is designed and fabricated in a 2.5-V 0.25-µm 4-metal-layer Si-Ge Bi-CMOS process. The 30-µm30-µm loop antenna located on the top-metal layer operates as an coil in an integrated mm-wave pulse generator. Each of on-chip pulse generators employing under-damped/over-damped conditions to produce mm-wave pulses includes an R-L-C circuit, a bipolar junction transistor (BJT) operated as a switch and a CMOS inverter chain circuit for shaping the rising edge of the input clock. Simulation results by ADS 2009 and HSPICE show that loop antenna' inductance and resistance at 80–120-GHz are 51 pH and 3 Ω, respectively. A simulation performance of an integrated 136 loop antenna array illustrates the variation of maximum radiation angles depending on different phase values between array's elements. By using an mm-wave power meter, a 90–140-GHz standard horn antenna and a Schottky diode detector, several measured radiation patterns of this loop antenna array chip are achieved. From the measurement result, we demonstrate the possibility of an integrated mm-wave pulse generator for the purpose of beam-forming by changing power supplies of inverter chains.

A fully differential high gain V-band three-stage transformer-coupled power amplifier (PA) is designed and implemented in 65 nm CMOS process. On-chip transformers which offer DC biasing for individual stages, extra stabilization mechanism, single-ended to differential conversion, and input/inter-stage/output matching are used to facilitate a compact amplifier design. The design and optimization methodologies of active and passive devices are presented. With a cascode configuration, the amplifier achieves a linear gain of 30.5 dB centered at 63.5 GHz and a -40 dB reverse isolation under a 1 V supply, which compares favorably to recent published V-band PAs. The amplifier delivers 9 dBm and 13 dBm saturation output power (Psat) under 1 V and 1.5 V supplies, respectively, and occupies a core chip area of 0.05 mm2. The measurement results validate a high gain and area-efficient power amplifier design methodology in deep-scaled CMOS for applications in millimeter-wave communication.

We present an 88 wavelength-routing switch (WRS) that monolithically integrates tunable wavelength converters (TWCs) and an 88 arrayed-waveguide grating. The TWC consists of a double-ring-resonator tunable laser (DRR TL) allowing rapid and stable switching and a semiconductor-optical-amplifier-based optical gate. Two different types of dry-etched mirrors form the laser cavity of the DRR TL, which enable integration of the optical components of the WRS on a single chip. The monolithic WRS performed 18 high-speed wavelength routing of a non-return-to-zero signal at 10 Gbit/s. The switching operation was demonstrated by simultaneously using two adjacent TWCs.

In this paper, a differential input/output linear MOS transconductor using an adaptively biasing technique is proposed. The proposed transconductor based on a differential pair is linearized by employing an adaptively biasing circuit. The linear characteristic of the individual differential output currents are obtained by introducing the adaptively biased currents to terminate the differential output terminals. Using the proposed technique, the common-mode rejection ration (CMRR) becomes high. Simulation results show that the proposed technique is effective for improvement of the linearity and other performances.

High-power protection switch utilizing a new stub/line selectable configuration is presented. By employing the proposed circuit topology, the insertion loss at receiving mode and the power handling capability at transmitting mode can be independently designed. Therefore, the proposed circuit is able to achieve low insertion loss at receiving mode while keeping high-power performance at transmitting mode. To verify this methodology, MMIC switch has been fabricated in Ka-band. The circuit has achieved the insertion loss of 2 dB, the isolation of 25 dB, and the power handling capability of 40 dBm at 5% bandwidth.

In this paper, we show the recent progress of photonic network technologies for the new generation network (NWGN). The NWGN is based on new design concepts that look beyond the next generation network (NGN) and the Internet. The NWGN will maintain the sustainability of our prosperous civilization and help resolve various social issues and problems by the use of information and communication technologies. In order to realize the NWGN, many novel technologies in the physical layer are required, in addition to technologies in the network control layer. Examples of cutting-edge physical layer technologies required to realize the NWGN include a terabit/s/port or greater ultra-wideband optical packet switching system, a modulation-format-free optical packet switching (OPS) node, a hybrid optoelectronic packet switching node, a packet-based reconfigurable optical add/drop multiplexer (ROADM) system, an optical packet and circuit integrated node system, and optical buffering technologies.

A new kind of 3D power divider based on a half-mode substrate integrated circular cavity (HSICC) is proposed. This novel power divider can reduce the size of a power divider based on normal substrate integrated circular cavity (SICC) by nearly a half. To verify the validity of the design method, a two-way X-band HSICC power divider using low temperature co-fired ceramic (LTCC) technology is designed, fabricated and measured.

Although larger scale integration enhances the practicability of superconducting Josephson circuits, several technical problems begin to emerge during its progress. One of the problems is the increase of current through a ground plane (ground current). Excess ground current produces additional magnetic field and reduces operation margins of the circuits, because superconducting Josephson devices are very sensitive to magnetic field. In this paper, we evaluate current distribution in a superconducting ground plane by means of both experiments and numerical calculation. We also verify two methods for suppressing the ground current. One is a slot structure in the ground plane, and the other is alignment of the current-extraction point. Suppression of the ground current is quantitatively evaluated.

In order to accelerate yield improvement in semiconductor manufacturing, it is important to prevent the root causes of product-specific failures, such as systematic defects and parametric defects, which are different for each product. We herein propose a method for the investigation of product-specific failures by estimating differences between the actual failing bit signatures (FBSs) and the predicted FBSs caused by random defects. In order to estimate these differences accurately, we have developed a novel algorithm by which to extract the critical area for each FBS. The total failure rate errors of FBSs are within 0.5% for embedded SRAMs. The proposed method identified the root causes of product-specific failures in 150 and 65 nm technology node products.

As great advancements have been made in CMOS process technology over the past 20 years, RF CMOS circuits operating in the microwave band have rapidly developed from component circuit levels to multiband/multimode transceiver levels. In the next ten years, it is highly likely that the following devices will be realized: (i) versatile transceivers such as those used in software-defined radios (SDR), cognitive radios (CR), and reconfigurable radios (RR); (ii) systems that operate in the millimeter-wave or terahertz-wave region and achieve high speed and large-capacity data transmission; and (iii) microminiaturized low-power RF communication systems that will be extensively used in our everyday lives. However, classical technology for designing analog RF circuits cannot be used to design circuits for the abovementioned devices since it can be applied only in the case of continuous voltage and continuous time signals; therefore, it is necessary to integrate the design of high-speed digital circuits, which is based on the use of discrete voltages and the discrete time domain, with analog design, in order to both achieve wideband operation and compensate for signal distortions as well as variations in process, power supply voltage, and temperature. Moreover, as it is thought that small integration of the antenna and the interface circuit is indispensable to achieve miniaturized micro RF communication systems, the construction of the integrated design environment with the Micro Electro Mechanical Systems (MEMS) device etc. of the different kind devices becomes more important. In this paper, the history and the current status of the development of RF CMOS circuits are reviewed, and the future status of RF CMOS circuits is predicted.

A broadband cruciform substrate integrated waveguide coupler is designed based on the planar circuit approach. The broadband property is obtained by widening the crossed region in the same way as rectangular waveguide cruciform couplers. As a result, a 3 dB coupler with fractional bandwidth of 30% is realized at 24 GHz.

This letter presents an analytical study of the reverse link Erlang capacity of 3G/Ad Hoc Integrated networks. In the considered integrated network, 3G networks and Ad Hoc networks operate over the same frequency band and hence cause interference to each other. The reverse link Erlang capacity is analyzed and discussed in two cases: Ad Hoc networks use and do not use power control.

High integration and low power operation of integrated circuits make noise sensitivity high. Therefore, it is important to reduce noise of circuits. A bias-offset transconductor is known as a linear transconductor. It is expected that noise sensitivity of the transconductor becomes higher due to improvement of linearity and reduction of power dissipation. This paper proposes a design method to reduce noise considering high linearity, reduction of power dissipation and small circuit size.

Post-wall waveguide with a linear array of reflection-canceling slot pairs and center-feed is designed to cancel the frequency dependent tilting of the main beam and enhance the bandwidth of the antenna boresight gain. The array is fed at the center of the waveguide from the backside; the length of the radiating waveguide is halved and the long line effect in traveling wave operation is suppressed. Authors establish the array design procedure in separate steps to reduce the computational load in the iterative optimization by using Ansoft HFSS simulator. A center-feed linear array as well as an end-feed equivalent with uniform excitation is designed for 25.6 GHz operation and measured. The measured performances confirm the design and the advantage of the centre-feed; a frequency independent boresight beam is observed and the frequency bandwidth for 3 dB gain reduction is enhanced by 1.5 times compared to the end-feed array.

A fast calculation tool for state-dependent capacitance of power distribution network is proposed. The proposed method achieves linear time-complexity, which can be more than four orders magnitude faster than a conventional SPICE-based capacitance calculation. Large circuits that have been unanalyzable with the conventional method become analyzable for more comprehensive exploration of capacitance variation. The capacitance obtained with the proposed method agrees SPICE-based method completely (up to 5 digits), and time-linearity is confirmed through numerical experiments on various circuits. The maximum and minimum capacitances are also calculated using average and variance estimation. Calculation times are linear time-complexity, too. The proposed tool facilitates to build an accurate macro model of an LSI.

This paper represents a low noise second harmonic oscillator using mutually synchronized Gunn diodes. A multi-layer MIC technology is adopted to reduce the circuit size of the oscillator. The oscillator consists of Gunn diodes, slot line resonators and strip lines. By embedding Gunn diodes in the slot line resonators, a harmonic RF signal can be generated very easily. The strip lines are used for the power combining output circuit. The shape of slot line resonator is square in order to achieve the low phase noise and the suppression of undesired harmonics. The second harmonic oscillator is designed and fabricated in K band. The output power is +8.89 dBm at the design frequency of 18.75 GHz (2f0) with the phase noise of -116.2 dBc/Hz at the offset frequency of 1 MHz. Excellent suppression of the undesired fundamental frequency signal (f0) of -33 dBc is achieved. Also, the circuit size is reduced by three-tenths relative to that of the previously proposed circuit.

A monolithic modulator driver IC based on InP HBTs with a new circuit topology -- called a functional distributed circuit (FDC) -- for over 80-Gb/s optical transmission systems has been developed. The FDC topology includes a wide-band amplifier designed using a distributed circuit, a digital function designed using a lumped circuit, and broadband impedance matching between the lumped circuit and distributed circuit to enable both wider bandwidth and digital functions. The driver IC integrated with a 2:1 multiplexing function produces 2.6-Vp-p (differential output: 5.2 Vp-p) and 2.4- Vp-p (differential output: 4.8 Vp-p) output-voltage swings with less than 450-fs and 530-fs rms jitter at 80 Gb/s and 90 Gb/s, respectively. To the best of our knowledge, this is equivalent to the highest data rate operation yet reported for monolithic modulator drivers. When it was mounted in a module, the driver IC successfully achieved electro-optical modulation using a dual-drive LiNbO3 Mach-Zehnder modulator up to 90 Gb/s. These results indicate that the FDC has the potential to realize high-speed and functional ICs for over-80-Gb/s transmission systems.

Post-wall waveguide slot arrays are potential candidates for millimeter-wave systems. The modeling of the post-walls by the equivalent solid-walls in terms of guided wavelength is indispensable for intensive optimization of slot design for reducing computational load. In the single mode waveguide slot arrays, the modeling errors of the post-wall waveguide by the solid-wall waveguide are serious especially for the transversely located slots. The S-parameter prediction errors become larger as we increase the height of the waveguide to utilize the low-loss advantage of the waveguide. The authors propose a novel post-wall waveguide structure, named as a connected post-wall (C-PW), to enhance the equivalence. The C-PW waveguide keeps enhanced equivalence to the solid-walls even for a larger substrate height. The predictions are confirmed by simulations and measurements. An 8-element linear array of reflection-cancelling slot pairs is designed by using the equivalent solid-wall model to demonstrate the feasibility of the simple design in the C-PW.

This paper introduces a new technique for electromagnetic immunity modeling of integrated circuits (ICs), compliant with industrial requirements and valid up to 3 GHz. A specific modeling flow is introduced, which makes it possible to predict the conducted immunity of an IC according to a given criterion, whatever its external environment. This methodology was validated through measurements performed on several devices.