The Satellite/Terrestrial Integrated mobile Communication System (STICS), which allows terrestrial mobile phones to communicate directly through a satellite, has been studied [1]. Satellites are unaffected by the seismic activity that causes terrestrial damage, and therefore, the STICS can be expected to be a measure that ensures emergency call connection. This paper first describes the basic characteristics of call blocking rates of terrestrial mobile phone systems in areas where non-functional base stations are geographically clustered, as investigated through computer simulations that showed an increased call blocking rate as the number of non-functional base stations increased. Further simulations showed that restricting the use of the satellite system for emergency calls only ensures the STICS's capacity to transmit emergency communications; however, these simulations also revealed a weakness in the low channel utilization rate of the satellite system [2]. Therefore, in this paper, we propose increasing the channel utilization rate with a priority channel framework that divides the satellite channels between priority channels for emergency calls and non-priority channels that can be available for emergency or general use. Simulations of this priority channel framework showed that it increased the satellite system's channel utilization rate, while continuing to ensure emergency call connection [3]. These simulations showed that the STICS with a priority channel framework can provide efficient channel utilization and still be expected to provide a valuable secondary measure to ensure emergency communications in areas with clustered non-functional base stations during large-scale disasters.

We are developing a fast Fourier transform (FFT) processor using high-speed and low-power single-flux-quantum (SFQ) circuits. Our main concern is the development of an SFQ butterfly processing circuit, which is the core processing circuit in the FFT processor. In our previous study, we have confirmed the complete operation of an integer-type butterfly processing circuit using the AIST 2.5 kA/cm$^{2}$ Nb standard process at the frequency of 25 GHz. In this study, we have designed an integer-type butterfly processing circuit using the AIST 10,kA/cm$^{2}$,Nb advanced process and confirmed its high-speed operation at the maximum frequency of 50,GHz.

Because dielectrics between active layers have low thermal conductivities, there is a demand to reduce the temperature increase in three-dimensional integrated circuits (3D ICs). This paper demonstrates that, in the design of 3D ICs, different layer assignments often lead to different temperature increases. Based on this observation, we are motivated to perform temperature-aware layer assignment. Our work includes two parts. Firstly, an integer linear programming (ILP) approach that guarantees a minimum temperature increase is proposed. Secondly, a polynomial-time heuristic algorithm that reduces the temperature increase is proposed. Compared with the previous work, which does not take the temperature increase into account, the experimental results show that both our ILP approach and our heuristic algorithm produce a significant reduction in the temperature increase with a very small area overhead.

For next generation planar lightwave circuit (PLC) devices, high function and high-density integration are required as well as downsizing and cost reduction. To realize these needs, high refractive index difference between a core and a clad $(Delta)$ is required. To use PLC for practical applications, silica-based PLC is one of the most attractive candidate. However, degradation of the optical properties and productivity occur when $Delta$ of the core becomes high. Thus, $Delta$ of most of the conventional PLC with GeO$_2$-SiO$_2$ core is designed less than 2.5%. In this paper, we report a silica-based ultra-high $Delta $ PLC with ZrO$_2$-SiO$_2$ core. 5.5%-$Delta$ ZrO$_2$-SiO$_2$ PLC has been realized with low propagation loss and basic characteristics has been confirmed. Potential of chip size reduction of the ZrO$_2$-SiO$_2$ PLC is shown.

Integrated InP polarization converters based on half-ridge structure are studied numerically. We demonstrate that the fabrication tolerance of the half-ridge structure can be extended significantly by introducing a slope at the ridge side and optimizing the thickness of the residual InGaAsP layer. High polarization conversion over 90% is achieved with the broad range of the waveguide width from 705 to 915~nm, corresponding to a factor-of-two or larger improvement in the fabrication tolerance compared with that of the conventional polarization converters. Finally we present a simple fabrication procedure of this newly proposed structure, where the thickness of the residual InGaAsP layer is controlled precisely by using a thin etch-stop layer.

A new wavelength-selective optical modulator was proposed and discussed. The modulator consists of three kinds of distributed Bragg reflectors (DBRs) integrated in a single straight waveguide. The waveguide can guide TE$_0$ and TE$_1$ modes, and an in-line Michelson interferometer is constructed by the three DBRs. An operation-wavelength wave among incident wavelength-division-multiplexed TE$_1$ guided waves is split into TE$_0$ and TE$_1$ guided waves by one of DBRs, and combined by the same DBR to be TE$_0$ output wave with interference after one of waves is phase-modulated. A modulator using an electro-optic (EO) polymer is designed, and the static performance was predicted theoretically. An operation principle was confirmed experimentally by a prototype device utilizing a thermo-optic effect instead of the EO effect.

An optoelectronic 32-bit serial-to-parallel converter with a novel conversion scheme and shared-trigger configuration has been developed for the label processing of 100-Gbps (25-Gbps $ imes 4 lambda)$ optical packets. No external optical trigger source is required to operate the converter, as the optical packet itself is used to perform self-triggering. Compared to prior optoelectronic label converters, the new device has a much higher gain even while converting labels at higher data rates, and exhibits tolerance to the voltage swing of received packets. The device response is presented together with the experimental demonstration of serial-to-parallel conversion for 4 different labels at 25 Gbps.

We describe wavelength-routed switching technology for 25-Gbit/s optical packets using a tunable transmitter that monolithically integrates a parallel-ring-resonator tunable laser and an InGaAlAs electro-absorption modulator (EAM). The transmitter provided accurate wavelength tunability with 100-GHz spacing and small output power variation. A 25-Gbit/s burst-mode optical-packet data was encoded onto the laser output by modulating the integrated EAM with a constant voltage swing of 2 V at 45$^{circ}$C. Clear eye openings were observed at the output of the 100 GHz-spaced arrayed-waveguide grating with error-free operation being achieved for all packets. The tunable transmitter is very promising for realizing a high-speed, large-port-count and energy-efficient wavelength-routing switch that enables the forwarding of 100-Gbit/s optical packets.

We have been developing a superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconductive strip ion detector (SSID) and a single-flux-quantum (SFQ) multi-stop time-to-digital converter (TDC). The SFQ multi-stop TDC can measure the time intervals between multiple input signals and directly convert them into binary data. In this study, we designed and implemented 24-bit SFQ multi-stop TDCs with a 3×24-bit FIFO buffer using the AIST Nb standard process (STP2), whose time resolution and dynamic range are 100ps and 1.6ms, respectively. The timing jitter of the TDC was investigated by comparing two types of TDCs: one uses an on-chip SFQ clock generator (CG) and the other uses a microwave oscillator at room temperature. We confirmed the correct operation of both TDCs and evaluated their timing jitter. The experimentally-obtained timing jitter is about 40ns and 700ps for the TDCs with and without the on-chip SFQ CG, respectively, for the measured time interval of 50µs, which linearly increases with increase of the measured time interval.

Recently, we proposed a new data-path architecture, named a large-scale reconfigurable data-path (LSRDP), based on single-flux-quantum (SFQ) circuits, to establish a fundamental technology for future high-end computers. In this architecture, a large number of SFQ floating-point units (FPUs) are used as core components, and their high performance and low power consumption are essential. In this research, we implemented an SFQ half-precision bit-serial floating-point multiplier (FPM) with a target clock frequency of 50GHz, using the AIST 10kA/cm2 Nb process. The FPM was designed, based on a systolic-array architecture. It contains 11,066 Josephson junctions, including on-chip high-speed test circuits. The size and power consumption of the FPM are 6.66mm × 1.92mm and 2.83mW, respectively. Its correct operation was confirmed at a maximum frequency of 93.4GHz for the exponent part and of 72.0GHz for the significand part by on-chip high-speed tests.

We present our design and operation of a 6-bit quasi-triangle voltage waveform generator comprising three circuit blocks; an improved variable Pulse Number Multiplier (variable-PNM), a Code Generator (CG), and a Double-Flux-Quantum Amplifier (DFQA). They are integrated into a single chip using a niobium Josephson junction technology. While the multiplication factor of our previous m-bit variable-PNM was limited between 2m-1 and 2m, that of the improved one is extended between 1 and 2m. Correct operations of the 6-bit variable-PNM are confirmed in low-speed testing with respect to the codes from the CG, whereas generation of a 6-bit, 0.20mVpp quasi-triangle voltage waveform is demonstrated with the 10-fold DFQA in high-speed testing.

In this paper, we present a pure hardware implementation of the advanced encryption standard (AES) with 8-bit data path with both encryption/decryption abilities for applications of wireless network. To achieve the requirements of low area resource and high throughput performance, the 8-bit AES design overlaps the MixColumns (MC) and ShiftRows (SR), Inverse MixColumns (IMC) and Inverse ShiftRows (ISR) operations in order to reduce the required clock cycles and critical path delay of transformations involved. The combinations of SB with ISB, MC with IMC, and SR with ISR can effectively reduce the area cost of the AES realization. We implement the AES processor in an ASIC chip. The design has the area cost of 4.3 k-gates with throughput of 72Mbps which can meet the throughput requirement of IEEE 802.11g wireless network standard. From the experimental results, we observe that our AES design has better performance compared with other previous designs.

Recently, it has been shown that electromagnetic radiation from electrical devices leaks internal information. Some investigations have shown that information leaks through the clock frequency and higher harmonic waves. Thus, previous studies have focused on the information leakage from information processing circuits. However, there has been little discussion about information leaks from peripheral circuits. In this paper, we focus on the oscillation frequency of the integrated RC oscillators. In this paper, we use a keyboard as a device that includes a RC oscillator. Then experiments observed information leaks caused by key inputs. Our experiments show that frequency fluctuations cause information leakages and clarify what information can be acquired from the fluctuation. Then, we investigate the possibility of information leaking from peripheral circuits through modulated signals which are radiated by the peripheral circuits.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

One of the most serious challenges facing the exponential performance growth in the information industry is a bandwidth bottleneck in inter-chip interconnects. We therefore propose a photonics-electronics convergence system with a silicon optical interposer. We examined integration between photonics and electronics and integration between light sources and silicon substrates, and we fabricated a conceptual model of the proposed system based on the results of those examinations. We also investigated the configurations and characteristics of optical components for the silicon optical interposer: silicon optical waveguides, silicon optical splitters, silicon optical modulators, germanium photodetectors, arrayed laser diodes, and spot-size converters. We then demonstrated the feasibility of the system by fabricating a high-density optical interposer by using silicon photonics integrated with these optical components on a single silicon substrate. As a result, we achieved error-free data transmission at 12.5 Gbps and a high bandwidth density of 6.6 Tbps/cm2 with the optical interposer. We think that this technology will solve the bandwidth bottleneck problem.

There is a relentless push for cost and size reduction in optical transmitters and receivers for fiber-optic links. Monolithically integrated optical chips in InP and Si may be a way to leap ahead of this trend. We discuss uses of integration technology to accomplish various telecommunications functions.

We have succeeded in demonstrating high-performance four-channel 25 Gb/s integrated receiver for 100 Gb/s Ethernet with a built-in spatial Demux optics and an integrated PD array. All components which configure to the Demux optics adhered to a prism. Because of the shaping accuracy for prism, the insertion loss was able to suppress to 0.8 dB with small size. The connection point of the package for high speed electrical signals was improved to decrease the transmission loss. The small size of 12 mm 17 mm 7 mm compact package with a side-wall electrical connector has been achieved, which is compatible with the assembly in CFP2 form-factor. We observed the sensitivity at average power of -12.1 dBm and the power penalty of sensitivity due to the crosstalk of less than 0.1 dB.

20-Gbps non return-to-zero (NRZ) – binary phase shift keying (BPSK) using the silicon Mach-Zehnder modulator is demonstrated and characterized. Measurement of a constellation diagram confirms successful modulation of 20-Gbps BPSK with the silicon modulator. Transmission performance is characterized in the measurement of bit-error-rate in accumulated dispersion range from -347 ps/nm to +334 ps/nm using SMF and a dispersion compensating fiber module. Optical signal-to-noise ratio required for bit-error-rate of 10-3 is 10.1 dB at back-to-back condition. It is 1.2-dB difference from simulated value. Obtained dispersion tolerance less than 2-dB power penalty for bit-error-rate of 10-3 is -220 ps/nm to +230 ps/nm. The symmetric dispersion tolerance indicates chirp-free modulation. Frequency chirp inherent in the modulation mechanism of the silicon MZM is also discussed with the simulation. The effect caused by the frequency chirp is limited to 3% shift in the chromatic dispersion range of 2 dB power penalty for BER 10-3. The effect inherent in the silicon modulation mechanism is confirmed to be very limited and not to cause any significant degradation in the transmission performance.

This paper describes a high-speed, robust, scalable, and low-cost feed-forward time amplifier that uses phase detectors and variable delay lines. The amplifier works by detecting the time difference between two rising input edges with a phase detector and adjusting the delay of the variable delay line accordingly. A test chip was designed and fabricated in 65 nm CMOS. The measured resulting performance indicates that it is possible to amplify time difference while maintaining high-speed operation.

A four-stage power amplifier (PA) with 10 GHz 1-dB bandwidth (56–66 GHz) is presented. The broadband performance is achieved owing to π-section interstage matching network. Three-stage-current-reuse topology is proposed to enhance efficiency. The amplifier has been fabricated in 65 nm digital CMOS. 18 dB power gain and 9.6 dBm saturated power (Psat) are achieved at 60 GHz. The PA consumes current of 50 mA at 1.2 V supply voltage, and has a peak power-added efficiency (PAE) of 13.6%. To the best of the authors' knowledge, this work shows the highest PAE among the reported CMOS PAs that covers the worldwide 9 GHz ISM millimeter-wave band with less-than-1.2 V supply voltage.