Optical buffering has been one of the major technical challenges in realizing optical packet switching routers and interconnects. We demonstrate a compact optical buffer module, comprising an InP 18 phased-array switch and a silica-based delay line circuit. The integrated delay line circuit is fabricated on the silica-based planar-lightwave circuit (PLC) platform, and has the ladder architecture for reducing the size. In addition, variable optical couplers are integrated to achieve effective power equalization. Tunable and uniform buffering of up to 21 ns is obtained with 3-ns temporal resolution.

We describe 25-Gb/s error-free transmission over multi-mode fiber (MMF) by using a transmitter based on a 1.3-µm lens-integrated surface-emitting laser (LISEL) and a CMOS laser-diode driver (LDD). It demonstrates 25-Gb/s error-free transmission over 30-m MMF under the overfilled-launch condition and over 150-m MMF with a power penalty less than 1.0 dB under the underfilled-launch condition.

This paper presents a novel CMOS readout circuit for satellite infrared time delay and integration (TDI) arrays. An integrate-while-read method is adopted, and a dead-pixel-elimination circuit for solving a critical problem of the TDI scheme is integrated within a chip. In addition, an adaptive charge capacity control method is proposed to improve the signal-to-noise ratio (SNR) for low-temperature targets. The readout circuit was fabricated with a 0.35-µm CMOS process for a 5004 mid-wavelength infrared (MWIR) HgCdTe detector array. Using the circuit, a 90% background-limited infrared photodetection (BLIP) is satisfied over a wide input range (∼200–330 K), and the SNR is improved by 11 dB for the target temperature of 200 K.

Large-signal-based nonlinear models are developed to analyze a variety of dynamic performances in a resonant tunneling diode (RTD) with peripheral circuits such as an integrated broad band bow-tie antenna, a bias circuit and a bias stabilizer circuit. Dynamic modes of the RTD are classified by the time-domain analysis with the model. On the basis of our model, we suggest a possibility to discuss a terahertz order oscillation mode control, and the ASK modulation in several tens Gbit/sec in the RTD with the broad band antenna. Validity of the model and analysis is shown by explaining measured results of modulated oscillation signals in fabricated triple-barrier RTDs.

In this paper, the research advances in silicon based millimeter wave and THz ICs in the State Key Laboratory of Millimeter Waves is reviewed, which consists of millimeter wave amplifiers, mixers, oscillators at Q, V and W and D band based on CMOS technology, and several research approaches of THz passive ICs including cavity and filter structures using SIW-like (Substrate Integrated Waveguide-like) guided wave structures based on CMOS and MEMs process. The design and performance of these components and devices are presented.

High frequency bands such as the 3-GHz band have received much attention as frequency resources for broadband mobile communication systems. Radio Frequency (RF) integrated antennas are considered to be useful as base station antennas in decreasing the feeding loss that is otherwise inevitable in high frequency bands and they ensure sufficient power for broadband transmission. One problem in actualizing RF integrated antennas is miniaturizing the duplexer, which is generally large, among the RF circuitry components. To downsize the duplexer, we consider separately locating the transmitter (Tx) and receiver (Rx) antennas. To suppress further the mutual coupling between the Tx and Rx antennas, we investigate a filter integrated antenna configuration. In this paper, we consider an aperture coupled patch antenna as the base antenna configuration and propose a new filter integrated antenna that comprises multiple rectangular elements installed between the coupling slot and radiation element of the Rx antenna. The simulation and measurement results confirm that the new antenna reduces the mutual coupling in the transmission frequency band up to 5.7 dB compared to the conventional slot coupled patch antenna configuration.

We propose an optical fiber connection navigation system that uses visible light communication for an integrated distribution module in a central office. The system realizes an accurate database, requires less skilled work to operate and eliminates human error. This system can achieve a working time reduction of up to 88.0% compared with the conventional work without human error for the connection/removal of optical fiber cords, and is economical as regards installation and operation.

In this paper, we designed and fabricated large scale micro-light-emitting-diode (LED) arrays and silicon driver for single chip device for realizing as prototypes of heterogeneous optoelectronic integrated circuits (OEICs). The large scale micro-LED arrays were separated by a dry etching method from mesa structure to 16,384 pixels of 128 128, each with a size of 15 µm in radius. Silicon driver was designed the additional bonding pad on each driving transistor for bonding with micro-LED arrays. Fabricated micro-LED arrays and driver were flip-chip bonded using anisotropic conductive adhesive.

A novel half mode elliptic substrate integrated waveguide (HMESIW) filter with bypass coupling substrate integrated circular cavity (BCSICC) is proposed and fabricated by using standard PCB technology. Due to the use of an elliptical waveguide cavity, the tolerance sensitivity of the filter is reduced. The filter optimizing procedure is therefore simplified. The measured results demonstrate its superior performance in tolerance sensitivity and show good agreements with the simulation results.

A novel type of optically clocked all-optical flip-flop based on a coupled-mode distributed Bragg reflector laser diode is proposed. The device operates as a bistable laser, where the two lasing modes at different wavelength are switched all-optically by injecting a clock pulse together with a set/reset signal. We employ an analytical model based on the two-mode coupled rate equations to verify the basic operation of the device numerically. Optically clocked flip-flop operation is obtained with a set/reset power of 0.60 mW and clock power of 1.8 mW. The device features simple structure, small footprint, and synchronized all-optical flip-flop operation, which should be attractive in the future digital photonic integrated circuits.

We propose a built-in planar lens for coupling light to a waveguide on a 2-D photonic crystal (PhC) membrane. A 2-D PhC waveguide with the built-in lens has been fabricated with AlGaAs. Improvement in coupling performance is discussed in comparison to waveguides with straight ends as cleaved.

We have developed two modulator driver ICs that are based on the functional distributed circuit (FDC) topology for over 40-Gb/s optical transmission systems using InP HBT technology. The FDC topology enables both a wide bandwidth amplifier and high-speed digital functions. The none-return-to-zero (NRZ) driver IC, which is integrated with a D-type flip-flop, exhibits 2.6-Vp-p (differential output: 5.2 Vp-p) output-voltage swings with a high signal quality at 43 and 50 Gb/s. The return-to-zero (RZ) driver IC, which is integrated with a NRZ to RZ converter, produces 2.4-Vp-p (differential output: 4.8 Vp-p) output-voltage swings and excellent eye openings at 43 and 50 Gb/s. Furthermore, we conducted electro-optical modulation experiments using the developed modulator driver ICs and a dual drive LiNbO3 Mach-Zehnder modulator. We were able to obtain NRZ and RZ clear optical eye openings with low jitters and sufficient extinction ratios of more than 12 dB, at 43 and 50 Gb/s. These results indicate that the FDC has the potential to achieve a large output voltage and create high-speed functional ICs for over-40-Gb/s transmission systems.

In this paper, we propose efficient sequential AES CCM architecture for the IEEE 802.16e. In the proposed architecture, only one AES encryption core is used and the operation of the CTR and the CBC-MAC is processed concurrently within one round. With this design approach, we can design sequential AES CCM architecture having 570 Mbps@102.4 MHz throughput and 1,397 slices at a Spartan3 3s5000 device.

We propose a novel metamaterial antenna that is based on loading a single complementary split ring resonator (CSRR) onto a substrate integrated waveguide (SIW) structure. Negative order and zeroth-order resonance can be observed in the proposed structure. These resonance modes are used to reduce the antenna size. In addition, a high quality (Q) factor of the CSRR-loaded SIW structure can minimize the radiation loss. The -1st, 0th, and 1st resonances are experimentally observed at 6.63, 13.68, and 20.31 GHz with maximum gains of 1.59, 3.97, 6.83 dBi, respectively. The electrical size of the antenna at the -1st resonance is only 42% of the resonance of a square microstrip patch antenna.

This paper presents a 65-nm CMOS 8-antenna array transmitter operating in 117–130-GHz range for short range and portable millimeter-wave (mm-wave) active imaging applications. Each antenna element is a new on-chip antenna located on the top metal. By using on-chip transformer, pulse output of each resistor-less mm-wave pulse generators (PG) are sent to each integrated antenna. To adjust pulse delays for the purpose of pulse beam-forming, a 7-bit digitally programmable delay circuit (DPDC) is added to each of PGs. Moreover, in order to dynamically adjust pulse delays among eight SW's outputs, we implemented on-chip jitter and relative skew measuring circuit with 20-bit digital output to achieve cumulative distribution (CDF) and probability density (PDF) functions from which DPDC's input codes are decided to align eight antenna's output pulses. Two measured radiation peaks after relative skew alignment are obtained at (θ; φ) angles of (-56; 0) and (+57; 0). Measurement results shows that beam-forming angles of the fully integrated antenna array can be adjusted by digital input codes and by the on-chip skew adjustment circuit for active imaging applications.

A readout circuit incorporating a pixel-level analog-to-digital converter (ADC) is studied for 2-dimensional microbolometer infrared focal plane arrays (IRFPAs). The integration time and signal-to-noise ratio (SNR) is improved using the current-mode bias and MSB skimming. The proposed pixel-level ADC is a two-step configuration, so its power consumption is very low. The readout circuit was designed using a 0.35 µm 2-poly 4-metal CMOS process for a 320240 microbolometer array with a pixel size of 35µm35µm. The noise equivalent temperature difference (NETD) was estimated to be 47 mK, with a power consumption of 390 nW for a pixel-level ADC.

With advances in communication technologies, network services provided via the Internet have become widely diversified, and people can use these services not only via wired networks but also via wireless networks. There are several wireless systems in practical use such as cellular, WiMAX and WiFi. Although these wireless network systems have developed independently of each other, they should be integrated for seamless access by users. However, each system uses an individual spectrum prescribed by law to avoid radio interference. To overcome such a situation, dynamic spectrum access technology is receiving much attention. We propose a dynamic spectrum assignment method in which a WiFi system temporarily uses a spectrum band of the WiMAX system in WiFi/WiMAX integrated networks to reduce call blocking probability of multimedia communication services. We confirm the effectiveness of the proposed method by simulation experiments.

Based on the substrate integrated waveguide (SIW) technology, a new type of varactor-tuned radial power divider has been developed with a single bias supply. The varactors are used as tuning elements and allow for a frequency agile behavior. In addition, bandwidth characteristics have been analysed with group-delay. It has been measured with a single bias supply ranging from 6 V to 12 V that the center frequency of the power divider can be adjusted from 6.6 GHz to 7.2 GHz (600 MHz, 11.5%) while maintaining a low insertion loss (< 1 dB) in the passband.

The noise performance of common source and cascode topology 60 GHz LNAs is analyzed and verified. The analysis result shows that the noise performance of the cascode topology is degraded at high frequency due to the inter-stage node capacitance. The analysis result is verified by experimental results. A three-stage LNA employing two noise-matched CS stages and a cascode stage is proposed. For comparison a conventional two-stage cascode LNA is also been studied with the measurement-based model. The measured results of the proposed LNA show that an input and output matching of less than -10 dB, a maximum gain of 9.7 dB and a noise figure (NF) of 3.2 dB are obtained with a power consumption of 30 mW from a 1.2-V supply voltage. Compared to the conventional cascode LNA, an improvement of 2.3-dB for NF and 1.9-dB for power gain are realized. Both the proposed and conventional LNAs are implemented in 65 nm CMOS process.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.