Post-wall waveguide slot arrays are potential candidates for millimeter-wave systems. The modeling of the post-walls by the equivalent solid-walls in terms of guided wavelength is indispensable for intensive optimization of slot design for reducing computational load. In the single mode waveguide slot arrays, the modeling errors of the post-wall waveguide by the solid-wall waveguide are serious especially for the transversely located slots. The S-parameter prediction errors become larger as we increase the height of the waveguide to utilize the low-loss advantage of the waveguide. The authors propose a novel post-wall waveguide structure, named as a connected post-wall (C-PW), to enhance the equivalence. The C-PW waveguide keeps enhanced equivalence to the solid-walls even for a larger substrate height. The predictions are confirmed by simulations and measurements. An 8-element linear array of reflection-cancelling slot pairs is designed by using the equivalent solid-wall model to demonstrate the feasibility of the simple design in the C-PW.

A composite right/left-handed transmission line (CRLH-TL) using substrate integrated waveguide (SIW) with floating-conductor (SIW-type CRLH-TL) for microwave and millimeter wave frequencies has been proposed by the authors. This paper proposes a new configuration that is shield type of the SIW-type CRLH-TL, which can suppress the radiation from the exposed floating-conductors, and shows that even if the shielded structure is used, the SIW-type CRLH-TL supports the LH mode as well as the prototype. Proposed CRLH-TL consists of a SIW with slot apertures (part 1), a dielectric film with floating-conductors (part 2) and a SIW without lower conductor (part 3). A shielded SIW-type CRLH-TL for X--K band (with wide LH mode bandwidth of 6 GHz and transition frequency of 16 GHz) that satisfies the balance condition is designed. Dispersion diagram and S-parameters are derived numerically, and typical field distributions of RH and LH transmission and the zeroth-order resonance are shown. Measured result agrees well with theoretical result, by considering the accuracy performance and loss factors of the fabricated CRLH-TL. Proposed CRLH-TL has advantage of simple manufacturing, because the parts 1--3 are composed of simple planar periodic structure. It is expected to be one of the basic structure of CRLH-TL or components such as LH coupler above 10 GHz or millimeter wave frequency.

A direct-conversion receiver integrated with the CMOS subharmonic frequency tripler (SFT) for V-band applications is designed, fabricated and measured using 0.13-µm CMOS technology. The receiver consists of a low-noise amplifier, a down-conversion mixer, an output buffer, and an SFT. A fully differential SFT is introduced to relax the requirements on the design of the frequency synthesizer. Thus, the operational frequency of the frequency synthesizer in the proposed receiver is only 20 GHz. The fabricated receiver has a maximum conversion gain of 19.4 dB, a minimum single-side band noise figure of 10.2 dB, the input-referred 1-dB compression point of -20 dBm and the input third order inter-modulation intercept point of -8.3 dB. It draws only 15.8 mA from a 1.2-V power supply with a total chip area of 0.794 mm0.794 mm. As a result, it is feasible to apply the proposed receiver in low-power wireless transceiver in the V-band applications.

We propose a CMOS circuit that can be used as an equivalent to resistors. This circuit uses a simple differential pair with diode-connected MOSFETs and operates as a high-resistance resistor when driven in the subthreshold region of MOSFETs. Its resistance can be controlled in a range of 1-1000 MΩ by adjusting a tail current for the differential pair. The results of device fabrication with a 0.35-µm 2P-4M CMOS process technology is described. The resistance was 13 MΩ for a tail current of 10 nA and 135 MΩ for 1 nA. The chip area was 105 µm110 µm. Our resistor circuit is useful to construct many high-resistance resistors in a small chip area.

An on-chip Charged Device Model (CDM) ESD protection method for RF ICs is proposed in a 0.13 µm RF process and evaluated by using very fast Transmission Line Pulse (vf-TLP) system. Key design parameters such as triggering voltage (Vt1) and the oxide breakdown voltage from the vf-TLP measurement are used to design input ESD protection circuits for a RF test chip. The characterization and the behavior of a Low Voltage Triggered Silicon Controlled Rectifier (SCR) which used for ESD protection clamp under vf-TLP measurements are also reported. The results measured by vf-TLP system showed that the triggering voltage decreased and the second breakdown current increased in comparison with the results measured by a standard 100 ns TLP system. From the HBM/ CDM testing, the RF test chip successfully met the requested RF ESD withstand level, HBM 1 kV, MM 100 V and CDM 500 V.

This paper presents a framework for formalizing and detecting feature interactions (FIs) in the emerging smart home domain. We first establish a model of home network system (HNS), where every networked appliance (or the HNS environment) is characterized as an object consisting of properties and methods. Then, every HNS service is defined as a sequence of method invocations of the appliances. Within the model, we next formalize two kinds of FIs: (a) appliance interactions and (b) environment interactions. An appliance interaction occurs when two method invocations conflict on the same appliance, whereas an environment interaction arises when two method invocations conflict indirectly via the environment. Finally, we propose offline and online methods that detect FIs before service deployment and during execution, respectively. Through a case study with seven practical services, it is shown that the proposed framework is generic enough to capture feature interactions in HNS integrated services. We also discuss several FI resolution schemes within the proposed framework.

This paper presents a design of a monolithic transformer using bond wires. The proposed transformer structure has several advantages such as high power handling and high efficiency. It shows that the measured insertion loss at the 1.9 GHz range is -1.54 dB (70%), which is higher than the spiral transformer of the same size. Also, it shows a phase error of less than 1 degree.

A filter integrated antenna configuration that suppresses the coupling signal from the transmitter (Tx) to receiver (Rx) base station antenna is investigated. We propose an aperture coupled patch antenna with multiple trapezoidal elements installed on the substrate of the Rx antenna between the radiation and feed layers in order to increase the bandwidth in the Rx band while maintaining low mutual coupling in the Tx band. The mutual coupling characteristics and the fractional bandwidth of the Rx antenna are presented as functions of the shape and width of the trapezoidal elements.

In this paper, the research advances in SIW-like (Substrate Integrated Waveguide-like) guided wave structures and their applications in the State Key Laboratory of Millimeter Waves of China is reviewed. Our work is concerned with the investigations on the propagation characteristics of SIW, half-mode SIW (HMSIW) and the folded HMSIW (FHMSIW) as well as their applications in microwave and millimeter wave filters, diplexers, directional couplers, power dividers, antennas, power combiners, phase shifters and mixers etc. Selected results are presented to show the interesting features and advantages of those new techniques.

We propose a novel 50 Mb/s optical transmitter fabricated in a 0.6 µm BiCMOS technology for automotive applications. The proposed VCSEL driver chip was designed to operate with a single supply voltage ranging from 3.0 V to 5.25 V. A fully integrated feedforward current control circuit is presented to stabilize the optical output power without any external components. The experimental results show that the optical output power can be stable within a 1.1 dB range and the extinction ratio greater than 14 dB over the automotive environmental temperature range of -40 to 105.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

We fabricated a high-speed wavelength tunable arrayed-waveguide grating (AWG) and an AWG integrated with optical switches using (Pb,La)(Zr,Ti)O3-(PLZT). PLZT has a high electro-optic (EO) coefficient, which means these devices have considerable potential for use in reconfigurable optical add drop multiplexers (ROADMs). The PLZT waveguides in this work have a rib waveguide structure with an effective relative index difference (Δ) of 0.65%. Both AWGs have 8 channels with a frequency spacing of 500 GHz. The fabricated wavelength tunable AWGs allows us to freely shift the output at a particular wavelength to an arbitrary port by applying voltages to 3 mm long electrodes formed on each of the waveguides. We confirmed that the maximum tuning range with driving voltage of 22 V was approximately 32 nm at 1.55 µm. With the integrated 8-ch PLZT waveguide switch array, we could also select the output port by setting the drive voltage applied to the switch array. 2 2 directional coupler switches were used for the switch array. The two devices exhibited insertion losses of 17 dB and 19 dB, adjacent crosstalk of -18.5 dB and -19.7 dB, and a maximum extinction ratio of 19.6 dB and 12.6 dB, respectively. The tuning speed of both devices was 15 ns and their physical sizes were 9.0 23.0 mm and 8.0 29.5 mm, respectively.

A 150 MS/s 10-bit MOS-inverter-based subranging analog-to-digital converter (ADC) dedicated to a high-speed low-power application is presented in this paper. A new time constant reduction technique is proposed in the multi-stage preamplifier design which aims to further increase the speed of the coarse ADC. A synchronized switch is introduced to minimize the sample-time mismatch in the interleaved architecture of fine ADCs. An internal pipelined scheme incorporating the double sampling and interleaving techniques in fine ADCs allows the ADC sample input signal to run on a consecutive clock, thus maximizing the throughput. The prototype ADC achieves 52 dB SNDR for a 10 MHz input frequency at 150 MS/s. Without calibration, the measured differential nonlinearity (DNL) is 0.5 LSB, while the integral nonlinearity (INL) is 0.9 LSB. The CMOS ADC is fabricated in a 0.35 µm CMOS technology, with an active area of 2.7 mm2, consuming only 178 mW from a single 3 V supply. Comparing technology normalized figure-of-merits, it achieves better power-speed efficiency than other similar types of ADCs.

In this paper, a compact channel thermal noise model for short-channel MOSFETs is presented and applied to the radio frequency integrated circuit (RFIC) design. Based on the analysis of the relationship among different short-channel effects such as velocity saturation effect (VSE), channel-length modulation (CLM), and carrier heating effect (CHE), the compact model for the channel thermal noise was analytically derived as a simple form. In order to simulate MOSFET's noise characteristics in circuit simulators, an appropriate methodology is proposed. The used compact noise model is verified by comparing simulated results to the measured data at device and circuit level by using 65 nm and 130 nm CMOS technologies, respectively.

Three-dimensional integrated circuits (3-D ICs), i.e., stacked dies, can alleviate the interconnect problem coming with the decreasing feature size and increasing integration density, and promise a solution to heterogenous integration. The vertical connection, which is generally implemented by the through-the-silicon via, is a key technology for 3-D ICs. In this paper, given 3-D circuit placement or floorplan results with white space reserved between blocks for inter-layer interconnections, we proposed methods for assigning inter-layer signal via locations. Introducing a grid structure on the chip, the inter-layer via assignment of two-layer chips can be optimally solved by a convex-cost max-flow formulation with signal via congestion optimized. As for 3-D ICs with three or more layers, the inter-layer signal via assignment is modeled as an integral min-cost multi-commodity flow problem, which is solved by a heuristic method based on the lagrangian relaxation. Relaxing the capacity constraints in the grids, we transfer the min-cost multi-commodity flow problem to a sequence of lagrangian sub-problems, which are solved by finding a sequence of shortest paths. The complexity of solving a lagrangian sub-problem is O(nntng2), where nnt is the number of nets and ng is the number of grids on one chip layer. The experimental results demonstrated the effectiveness of the method.

We identify a broadband equivalent circuit of an on-chip self-complementary antenna integrated with a µm-sized semiconductor mesa structure whose circuit elements can be interpreted by using closed-form analysis. Prior to the equivalent circuit analysis, an electromagnetic simulation is done to investigate frequency independency of the input impedance for the integrated self-complementary antenna in terahertz range.

We have proposed a tunable laser with silica-waveguide ring resonators. In this tunable laser, a semiconductor optical amplifier was passively aligned and mounted onto a silica-waveguide substrate. The ring resonators can be tuned by controlling their temperatures using the thermo optic heaters formed on them, and there are no mechanically moving parts. Thus, they are sufficiently stable and reliable for practical use. Our tunable laser exhibits a high fiber-output power of more than 15 dBm and a wide tunable range of 60 nm (L-band, 50 GHz spacing, 147 channels). Moreover, a tunable laser with a much wider tunable range of 96 nm using 100-GHz-FSR ring resonators is also reported.

This paper reviews our recent progress on arrayed waveguide gratings (AWGs) using super-high-Δ silica-based planar lightwave circuit (PLC) technology and their application to integrated optical devices. Factors affecting the chip size of AWGs and the impact of increasing relative index difference Δ on the chip size are investigated, and the fabrication result of a compact athermal AWG using 2.5%-Δ silica-based waveguides is presented. As an application of super-high-Δ AWGs to integrated devices, a flat-passband multi/demultiplexer consisting of an AWG and cascaded MZIs is presented.

To improve product yield in high-product-mix semiconductor manufacturing, it is important to estimate the systematic yield inherent to each product and to extract problematic products that have low systematic yields. We propose a simplified and available yield model using a critical area analysis. This model enables the extraction of problematic products by the relationship between actual yields and the short sensitivities of the products. Furthermore, we present an enterprise-wide yield management system using this model and some useful applications. As a result, the system increases the efficiency of the yield management and enhancement dramatically.

In this paper, we suggest a method of analyzing the post-wall waveguide (PWW) or the substrate integrated waveguide (SIW) by applying the analytical technique of the H-plane waveguide discontinuities based on the planar circuit approach. The analytical procedure consists of the derivation of the mode impedance matrices for regular-shaped circuits and the short-circuiting operation on fictitious ports arranged at the peripheries of the metallic posts. First, a straight section of the PWW is treated as an example and the analytical method for the calculation of the S-parameters is described in detail. Then the attenuation and phase constants of the PWW are computed with the aid of the Thru-Reflect Line (TRL) calibration technique. Next, the analytical method is applied to the design of two types of right-angled corners. The analysis and the design results are verified using an em-simulator (HFSS).