This work presents a new sigma-delta modulator (SDM) architecture for a wide bandwidth receiver. This architecture contains dual-bandwidth for W-CDMA and GSM system applications. Low-distortion swing-suppressing SDM and interpolative SDM cascaded units are used together. Using the low-distortion swing-suppressing technique, the resolution can be improved even under non-linearity effects. The interpolative SDM extends the signal bandwidth and represses the high-band noise. The SDM used in the W-CDMA and GSM applications was designed and simulated using 0.25-µm 1P5M CMOS technology. The simulated peak SNDR of W-CDMA and GSM are 72/70 dB and 82/84 dB in Low-IF/Zero-IF standards.

A linear voltage-to-current convertor without current mirror circuit is proposed for low distortion applications employing short channel MOSFET's. Twin current sources and current sinks pair of MOSFET's having the same drain-source voltage are employed for a substitute of the current mirror circuits, in order to eliminate the channel length modulation factor of the short channel MOSFET's. HSPICE simulation is shown in order to evaluate the proposed circuits. As an application, a low distortion OTA is realized by employing the proposed linear voltage-to-current convertor with short channel MOSFET's.

We have developed InGaP-channel field effect transistors (FETs) with high breakdown voltages that can be fabricated by using conventional GaAs FET fabrication processes. The buffer and barrier layers were also optimized for the realization of high-voltage operation. The InGaP-channel FET has an extremely high on-state drain-to-source breakdown voltage of over 40 V, and a gate-to-drain breakdown voltage of 55 V. This enabled high-voltage large-signal operation at 40 V. The third-order intermodulation distortion of the InGaP channel FETs was 10-20 dB lower than that of an equivalent GaAs-channel FET, due to the high operating voltage.

This paper proposes a low-distortion noise canceller and its learning algorithm which is robust against crosstalk and is applicable for continuous sounds. The proposed canceller consists of two stages: cancellation of the crosstalk and cancellation of the noise. A recursive filter reduces the number of computations for noise cancellation stage. Separate filters for the adaptation and the filtering are introduced for crosstalk cancellation. Computer simulations show 10 dB improvement of the error power.

A 100 W, low distortion AlGaAs/GaAs heterostructure FET has been developed for CDMA cellular base stations. This FET employs the longest gate finger ever reported of 800 µm to shrink the chip size. The size of the chip and the package are miniaturized to 1.242.6 mm2 and 17.4 24.0 mm2, respectively. The developed FET exhibits 100 W (50 dBm) saturation output power, and 11.5 dB power gain at 1 dB gain compression at 2.1 GHz. The third-order intermodulation distortion and the power-added efficiency under the two-tone test condition (Δf=1 MHz) are -35 dBc and 24%, respectively at 42 dBm output power, that is 8 dB back off from the saturation power.

We have demonstrated the single-chip RF front-end GaAs MMIC for the Japanese Personal Handy-phone System. It has a high efficiency HPA, a T/R switch, a LNA and a low-distortion down converter mixer. The IC employs a negative voltage generator for use of single voltage DC power supply. The HPA provides an output power of 21.5 dBm, with an ACPR of 55 dBc and an efficiency of 35%. The LNA has a noise figure of 1.6 dB and a gain of 14 dB with current of 2.3 mA. The newly developed active cascode FET mixer has a high IIP3 of 1 dBm with a high conversion gain of 10 dB and low consumption current of 2.3 mA. The IC is characterized by high performance for RF front-end of PHS handheld terminals. The IC is available in a 7.0 mm6.4 mm1.1 mm plastic package.

Two approaches to the design of resonant-type switches with low distortion characteristics operating at a 2-V power supply voltage have been proposed for use in the 1. 9-GHz-band personal handy phone system (PHS). One approach is to use three stacked FETs at the receiver side. They are composed of a dual-gate FET and a single-gate FET. An insertion loss of 0. 41 dB and an isolation of 44. 0 dB were obtained at 1. 9 GHz. A third-order distortion value of -52 dBc was achieved at 19 dBm output power. Another approach is to insert a capacitor in the resonator. A third-order distortion of -49 dBc at 19-dBm output power when two stacked FETs were used at the receiver side. The layout area of the resonator is drastically reduced as compared with the above-mentioned case.

A high power amplifier module has been developed for large cell base station in digital cordless system. For PHS application, this module exhibited Pout of 38 dBm with low ACP of -72 dBc (at 600 kHz offset point) and a power gain of 33 dB at a supply voltage of 9 V and a frequency range of 1890-1923 MHz. In order to realize this ultra low distortion performance, power FETs have been designed as considering high breakdown voltage and thermal stability. Power divider/combiner circuits, which have the advantages of low transmission loss and a function of controlling second harmonic, have been introduced. Moreover, a novel module package with features of low cost and good processing precision has been proposed.

A GaAs power MESFET amplifier with a low-distortion, 10-dB gain-variable attenuator has been developed for 1. 9-GHz Japanese personal handy phone system (PHS). Independently of its gain, a very low 600-kHz adjacent channel leakage power (ACP) with sufficient output power was attained. In single low 2. 4-V supply operation, an output power of 21. 1 dBm, a low dissipated current of 157 mA and a high power-added efficiency (PAE) of 37. 2% were obtained with an ACP of -55 dBc.

A GaAs power amplifier IC has been developed for 1. 9-GHz digital mobile communication applications, such as the handsets of the Japanese personal handy phone system (PHS), which was assembled into a very small 0. 012-cc surface mount plastic package. This power amplifier using refractory WNx/W self-aligned gate MESFETs with p-pocket layers can operate with high efficiency and low distortion with a single 3-V supply. A very low dissipated current of 119 mA was obtained with an output power of 21. 1 dBm and a low 600-kHz adjacent channel leakage power (ACP) of -63 dBc for π/4-shifted quadrature phase shift keying (QPSK) modulated input.

Characteristics of a distortion, gain and efficiency of a power amplifier grow worse extremely by different phases of the load reflection coefficient when load impedances of the power amplifier are far from 50 Ω. It was found that the value of the distortion, gain and efficiency showed the tradeoff behavior when the phase of the reflection coefficient was different in 180 degrees. Therefore we have proposed new two- and four-parallel unit power amplifiers combined in 90 degree and 45 degree different phases each in order to accomplish low distortion and high efficiency in wide range of load impedances without an isolator. We studied the power amplifiers by simulation based on experiments and realized an amplifier in that adjacent channel leakage power of π/4-DQPSK modulation (for Japan's digital cellular system) is less than -45 dBc and efficiency is over 45% in range of load VSWR less than 3.

The application of pulse-doped GaAs MESFET's to a power amplifier module is discussed in this paper. The epitaxial layer structure was redesigned to have a dual pulse-doped structure for power applications, achieving a sufficient gate-drain brakdown voltage with excellent linearity. The measured load-pull characteristics of the redesigned device for the minimum power consumption design was presented. This device was shown to have almost twice the power-added efficiency of a conventional ion-implanted GaAs MESFET. Two kinds of power amplifiers were designed and fabricated, achieving Pout of 28.6 dBm at IM3 of -40 dBc with Pdc of 8 W and Pout of 33.0 dBm at IM3 of -40 dBc with Pdc of 32 W, respectively.

As current-voltage characteristics of GaAs MESFET differ from those of BJT and MOSFET and n-channel FET is only practically in use, the development of GaAs MESFET analog integrated circuits is left behind. In this paper, two circuit techniques to improve the performance of GaAs MESFET analog circuits are provided. The one is to realize a high impedance active load circuit which dose not need CMFB (Common Mode Feed Back) to achieve stable DC biasing point. The other is to cancel the harmonic destortion caused by nonlinear characteristics of GaAs MESFETs. As an application example of the proposed circuits, biquad low-pass and band-pass filters are realized and simulated by HSPICE to verify the validity of the proposed method.