With the scaling of CMOS technology into the nanometer regime, the overshooting effect is more and more obvious and has a significant influence to gate delay and power consumption. Recently, researchers have already proposed the overshooting effect models for an inverter. However, the accurate overshooting effect model for multiple-input gates is seldom presented and the existing technology to reduce a multiple-input gate to an inverter is not useful when modeling the overshooting effect for multiple-input gates. Therefore, modeling the overshooting effect for multiple-input gates is proposed in this paper. Firstly, a formula-based model is presented for the overshooting time of 2-input NOR gate. Then, more complicated methods are given to calculate the overshooting time of 3-input NOR gate and other multiple-input gates. The proposed model is verified to have a good agreement, within 3.4% error margin, compared with SPICE simulation results using CMOS 32nm PTM model.

An on-chip soft-start circuit based on a switched-capacitor for DC-DC switching regulator is presented. A ramp-voltage, which is generated by a switched-capacitor, is used to make pulse width slowly increase from zero, in order to eliminate the inrush current and the overshoot voltage during start-up. The post simulation results show that the regulator soft starts well with the proposed soft-start circuit.

Conventional kernel prefetching schemes have focused on taking advantage of sequential access patterns that are easy to detect. However, it is observed that, on random and even sequential references, they may cause performance degradation due to inaccurate pattern prediction and overshooting. To address these problems, we propose a novel approach to work with existing kernel prefetching schemes, called Reference Pattern based kernel Prefetching (RPP). The RPP can reduce negative effects of existing schemes by identifying one more reference pattern, i.e., looping, in addition to random and sequential patterns and delaying starting prefetching until patterns are confirmed to be sequential or looping.

A simple analytical model based on Delayed Quadratic (DQ) Transfer Function approximation is proposed for estimating waveforms of inductive single-line interconnects in VLSI's. An expression for overshoot voltage is derived by the model within 17% error for the line width less than 10 times the minimum line width and typical input signal. A delay expression is also proposed within 15% for the same condition. The strength of the inductive effect is shown to be expressed by a closed-form expression, A=2(L(CT+0.5C))1/2/(RT(CT+CJ)+RTC+RCT+0.4RC). By using the criteria, a scaling trend of inductive effects in VLSI's is discussed. It is shown that the inductive effect of single-line, minimum-width VLSI interconnect peaks off at 90 nm based on the ITRS predicted parameters.

The modeling of gate delays has always been one of the most difficult and market-sensitive works. In submicron designs, the second-order effects such as the input-to-output coupling capacitance have a significant influence on gate delay as shown in this paper. However, the accurate analysis of the input-to-output coupling capacitance effect has not been presented in previous research. In this paper, an analytical model for the influence of the input-to-output coupling capacitance on CMOS inverter delay is proposed, in which a novel algorithm for computing overshooting time is given. Experimental results show good agreement with Spice simulations.

Transitional fundamental frequency (F0) characteristics comprise a crucial part of F0 dynamics in singing. This paper examines the F0 characteristics during the note transition period. An analysis of the singing voice of a professional baritone strongly suggests that asymmetries exist in the mechanisms used for controlling rising and falling. Specifically, the F0 contour in rising transitions can be modeled as a step response from a critically-damped second-order linear system with fixed average/maximum speed of change, whereas that in falling transitions can be modeled as a step response from an underdamped second-order linear system with fixed transition time. The validity of the model is examined through auditory experiments using synthesized singing voice.

The full-band Monte Carlo technique is currently the most accurate device simulation method, but its usefulness is limited because it is very CPU intensive. This work describes efficient algorithms in detail, which raise the efficiency of the full-band Monte Carlo method to a level where it becomes applicable in the device design process beyond exemplary simulations. The k-space is discretized with a nonuniform tetrahedral grid, which minimizes the discretization error of the linear energy interpolation and memory requirements. A consistent discretization of the inverse mass tensor is utilized to formulate efficient transport parameter estimators. Particle scattering is modeled in such a way that a very fast rejection technique can be used for the generation of the final state eliminating the main cause of the inefficiency of full-band Monte Carlo simulations. The developed full-band Monte Carlo simulator is highly efficient. For example, in conjunction with the nonself-consistent simulation technique CPU times of a few CPU minutes per bias point are achieved for substrate current calculations. Self-consistent calculations of the drain current of a 60nm-NMOSFET take about a few CPU hours demonstrating the feasibility of full-band Monte Carlo simulations.

MOSFETs with sub-0.1 µm gate length were fabricated, and their low temperature operation was investigated. The drain current for drain voltage of 2 V increased monotonously as temperature was lowered to 15 K without an influence of the freeze-out effect. Moreover, the increase in the drain current was enhanced by the gate length reduction. The hot-carrier effect at low temperature was also investigated. Impact-ionization decreased as temperature was lowered under the condition of drain voltage 2 V. The decreasing ratio was enhanced as gate length became shorter. We consider this phenomenon is attributed to the non-steady-stationary effect. As a result, device degradation by DC stressing was reduced at 77 K in comparison with room temperature. In the case of 0.1 µm MOSFET, drain current was not degraded in condition of DC stress with gate- and drain-voltage was 1.5 V.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

We investigated the impact of velocity overshoot effect on collector signal delay of bipolar devices by using Monte Carlo simulation method. We found that insertion of an i-layer (lightly doped, intrinsic layer) between base and collector can increase the delay, but the strength of this effect is a function of the i-layer thickness. When the i-layer becomes thinner, the problem of increasing delay seems to disappear. This recovery of delay is realised with a mechanism which is completely different from that in drift-diffusion model.

The velocity overshoot and hot carrier effects in thin-film SOI-nMOSFETs have been studied using a two-dimensional device simulator based on the energy transport model. It has been found that the velocity overshoot effect in a nearly-intrinsic device becomes pronounced in the short channel region because of their high carrier mobility. The distribution of the electron velocity in a 0.2 µm channel length SOI device shows that the velocity overshoot takes place over the whole channel region, which enhances the drive capability significantly. The behaviors of hot carriers injected into the gate oxide and the back oxide have been simulated for the first time by using the energy distribution functions of electrons and holes at the SOI-SiO2 interface and solving the current continuity equation in the oxide layer. It has been found that hot carriers are injected not only into the gate oxide but also into the back oxide, which can degrade hot-carrier reliability in small-featured thin-film SOI-MOSFETs.