The steady-state and convergence performances are important indicators to evaluate adaptive algorithms. The step-size affects these two important indicators directly. Many relevant scholars have also proposed some variable step-size adaptive algorithms for improving performance. However, there are still some problems in these existing variable step-size adaptive algorithms, such as the insufficient theoretical analysis, the imbalanced performance and the unachievable parameter. These problems influence the actual performance of some algorithms greatly. Therefore, we intend to further explore an inherent relationship between the key performance and the step-size in this paper. The variation of mean square deviation (MSD) is adopted as the cost function. Based on some theoretical analyses and derivations, a novel variable step-size algorithm with a dynamic limited function (DLF) was proposed. At the same time, the sufficient theoretical analysis is conducted on the weight deviation and the convergence stability. The proposed algorithm is also tested with some typical algorithms in many different environments. Both the theoretical analysis and the experimental result all have verified that the proposed algorithm equips a superior performance.

The application of millimeter wave (mmWave) directional transmission technology in high-speed railway (HSR) scenarios helps to achieve the goal of multiple gigabit data rates with low latency. However, due to the high mobility of trains, the traditional initial access (IA) scheme with high time consumption is difficult to guarantee the effectiveness of the beam alignment. In addition, the high path loss at the coverage edge of the millimeter wave remote radio unit (mmW-RRU) will also bring great challenges to the stability of IA performance. Fortunately, the train trajectory in HSR scenarios is periodic and regular. Moreover, the cell-free network helps to improve the system coverage performance. Based on these observations, this paper proposes an efficient IA scheme based on location and history information in cell-free networks, where the train can flexibly select a set of mmW-RRUs according to the received signal quality. We specifically analyze the collaborative IA process based on the exhaustive search and based on location and history information, derive expressions for IA success probability and delay, and perform the numerical analysis. The results show that the proposed scheme can significantly reduce the IA delay and effectively improve the stability of IA success probability.

Network Functional Virtualization (NFV) is a high-performance network interconnection technology that allows access to traditional network transport devices through virtual network links. It is widely used in cloud computing and other high-concurrent access environments. However, there is a long delay in the introduction of software NFV solutions. Other hardware I/O virtualization solutions don't scale very well. Therefore, this paper proposes a virtualization implementation method on 100Gbps high-speed Field Programmable Gate Array (FPGA) network accelerator card, which uses FPGA accelerator to improve the performance of virtual network devices. This method uses the single root I/O virtualization (SR-IOV) technology to allow 256 virtual links to be created for a single Peripheral Component Interconnect express (PCIe) device. And it supports data transfer with virtual machine (VM) in the way of Peripheral Component Interconnect (PCI) passthrough. In addition, the design also adopts the shared extensible queue management mechanism, which supports the flexible allocation of more than 10,000 queues on virtual machines, and ensures the good isolation performance in the data path and control path. The design provides high-bandwidth transmission performance of more than 90Gbps for the entire network system, meeting the performance requirements of hyperscale cloud computing clusters.

This paper presents a channel operating margin (COM) based high-speed serial link optimization using machine learning (ML). COM that is proposed for evaluating serial link is calculated at first and during the calculation several important equalization parameters corresponding to the best configuration are extracted which can be used for the ML modeling of serial link. Then a deep neural network containing hidden layers are investigated to model a whole serial link equalization including transmitter feed forward equalizer (FFE), receiver continuous time linear equalizer (CTLE) and decision feedback equalizer (DFE). By training, validating and testing a lot of samples that meet the COM specification of 400GAUI-8 C2C, an effective ML model is generated and the maximum relative error is only 0.1 compared with computation results. At last 3 link configurations are discussed from the view of tradeoff between the link performance and cost, illustrating that our COM based ML modeling method can be applied to advanced serial link design for NRZ, PAM4 or even other higher level pulse amplitude modulation signal.

In this paper, a reference-voltage self-selected pseudo-differential sensing scheme suitable for single-ended SRAM is proposed. The proposed sensing scheme can select different reference voltage according to the offset direction. With the employment of the new sensing scheme, the swing of the read bit-line in the read operation is reduced by 74.6% and 45.5% compared to the conventional domino and the pseudo-differential sense amplifier sensing scheme, respectively. Therefore, the delay and power consumption of the read operation are significantly improved. Simulation results based on a standard 55nm CMOS show that compared with the conventional domino and pseudo-differential sensing schemes, the sensing delay is improved by 66.4% and 47.7%, and the power consumption is improved by 31.4% and 22.5%, respectively. Although the area of the sensing scheme is increased by 50.8% compared with the pseudo-differential sense amplifier sensing scheme, it has little effect on the entire SRAM area.

This paper describes a method to evaluate the modulated waveforms output by a high-speed external phase modulator over a wide wavelength range by using linear optical sampling (LOS) and a wavelength-swept light source. The phase-modulated waveform is sampled by LOS together with the reference signal before modulation, and the modulation waveform is observed by removing the phase noise of the light source extracted from the reference signal. In this process, the frequency offset caused by the optical-path length difference between the measurement and reference interferometers is removed by digital signal processing. A pseudo-random binary-sequence modulated signal is observed with a temporal resolution of 10ps. We obtained a dynamic range of ∼40dB for the measurement bandwidth of 10 nm. When the measurement bandwidth is expanded to entire C-Band (∼35nm), the dynamic ranges of 37∼46dB were observed, depending on the wavelengths. The measurement time was sub-seconds throughout the experiment.

Environmental power generation devices such as solar cells are used as power sources for IoT devices. Due to the large internal resistance of such power source, LSIs in the IoT devices may malfunction when the LSI operates at high speed, a large current flows, and the voltage drops. In this paper, a standard cell library of stacked structured cells is proposed to increase the delay of logic circuits within the range not exceeding the clock cycle, thereby reducing the maximum current of the LSIs. We show that the maximum power consumption of LSIs can be reduced without increasing the energy consumption of the LSIs.

Observed results of arc discharges generated between the brush and commutator are reported. The motion of the arc discharges was observed by a high-speed camera. The brush and commutator were installed to an experimental device that simulated the rotational motion of a real DC motor. The aim of this paper is to investigate the occurring position, dimensions, and moving characteristics of the arc discharges by means of high-speed imaging. Time evolutions of the arc voltage and current were measured, simultaneously. The arc discharges were generated when an inductive circuit was interrupted. Circuit current before interruption was 4A. The metal graphite or graphite brush and a copper commutator were used. Following results were obtained. The arc discharge was dragged on the brush surface and the arc discharge was sticking to the side surface of the commutator. The positions of the arc spots were on the end of the commutator and the center of the brush in rotational direction. The dimensions of the arc discharge were about 0.2 mm in length and about 0.3 mm in width. The averaged arc voltage during arc duration became higher and the light emission from the arc discharge became brighter, as the copper content of the cathode decreased.

Dependences of arc duration D and contact gap at arc extinction d on contact opening speed v are studied for break arcs generated in a 48VDC resistive circuit at constant contact opening speeds. The opening speed v is varied over a wide range from 0.05 to 0.5m/s. Circuit current while electrical contacts are closed I0 is varied to 10A, 20A, 50A, 100A, 200A, and 300A. The following results were obtained. For each current I0, the arc duration D decreased with increasing contact opening speed v. However, the D at I0=300A was shorter than that at I0=200A. On the other hand, the contact gap at arc extinction d tended to increase with increasing the I0. However, the d at I0=300A was shorter than that at I0=200A. The d was almost constant with increasing the v for each current I0 when the I0 was lower than 200A. However, the d became shorter when the v was slower at I0=200A and 300A. At the v=0.05m/s, for example, the d at I0=300A was shorter than that at I0=100A. To explain the cause of the results of the d, in addition, arc length just before extinction L were analyzed. The L tended to increase with increasing current I0. The L was almost constant with increasing the v when the I0 was lower than 200A. However, when I0=200A and 300A, the L tended to become longer when the v was slower. The characteristics of the d will be discussed using the analyzed results of the L and motion of break arcs. At higher currents at I0=200A and 300A, the shorter d at the slowest v was caused by wide motion of the arc spots on contact surfaces and larger deformation of break arcs.

In conclusion, an initialization method has been introduced and studied to improve the SET speed in PCM. Before experiment verification, a two-dimensional finite analysis is used, and the results illustrate the proposed method is feasible to improve SET speed. Next, the R-I performances of the discrete PCM device and the resistance distributions of a 64 M bits PCM test chip with and without the initialization have been studied and analyzed, which confirms that the writing speed has been greatly improved. At the same time, the resistance distribution for the repeated initialization operations suggest that a large number of PCM cells have been successfully changed to be in an intermediate state, which is thought that only a shorter current pulse can make the cells SET successfully in this case. Compared the transmission electron microscope (TEM) images before and after initialization, it is found that there are some small grains appeared after initialization, which indicates that the nucleation process of GST has been carried out, and only needs to provide energy for grain growth later.

In order to enhance the fifth generation (5G) mobile communication system further toward 5G Evolution, high bit-rate transmission using high SHF bands (28GHz or EHF bands) should be more stable even in high-mobility environments such as high speed trains. Of particular importance, dynamic changes in the beam direction and the larger Doppler frequency shift can degrade transmission performances in such high frequency bands. Thus, we conduct the world's first 28 GHz-band 5G experimental trial on an actual Shinkansen running at a speed of 283km/h in Japan. This paper introduces the 28GHz-band experimental system used in the 5G experimental trial using the Shinkansen, and then it presents the experimental configuration in which three base stations (BSs) are deployed along the Tokaido Shinkansen railway and a mobile station is located in the train. In addition, transmission performances measured in this ultra high-mobility environment, show that a peak throughput of exceeding 1.0Gbps and successful consecutive BS connection among the three BSs.

This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.

Silver electrical contacts were separated at constant opening speed in a 200V-500VDC/10A resistive circuit. Break arcs were extinguished by magnetic blowing-out with transverse magnetic field of a permanent magnet. The permanent magnet was appropriately located to simplify the lengthened shape of the break arcs. Magnetic flux density of the transverse magnetic field was varied from 20 to 140mT. Images of the break arcs were observed from the horizontal and vertical directions using two high speed cameras simultaneously. Arc length just before extinction was analyzed from the observed images. It was shown that shapes of the break arcs were simple enough to trace the most part of paths of the break arcs for all experimental conditions owing to simplification of the shapes of the break arcs by appropriate arrangement of the magnet. The arc length increased with increasing supply voltage and decreased with increasing magnetic flux density. These results will be discussed in the view points of arc lengthening time and arc lengthening velocity.

The authors have been investigating the deterioration process of Au-plated slip-ring and Ag-Pd brush system with lubricant to realize stable and long lifetime. Through the past tests, it can be made clear that lubricant is very important for long lifetime, and a simple model of the deterioration process was proposed. However, it is still an issue how the lubricant is deteriorated and also what the relation between lubricant deterioration and contact voltage behavior is. In this paper, the contact voltage waveforms were regularly recorded during the test, and analyzed to obtain the time change of peak voltage and standard deviation during one rotation. Based on these results, it is discussed what happens at the interface between ring and brush with the lubricant. And the following results are made clear. The fluctuation of voltage waveforms, especially peaks of pulse-like fluctuation more easily occurs for minus rings than for plus rings. Further, peak values of the pulse-like fluctuation rapidly decreases and disappear at lower rotation speed as mentioned in the previous works. In addition, each peaks of the pulse-like fluctuation is identified at each position of the ring periphery. From these results, it can be assumed that lubricant film exists between brush and ring surface and electric conduction is realized by tunnel effect. In other words, it can be made clear that the fluctuation would be caused by the lubricant layer, not only by the ring surface. Finally, an electric conduction model is proposed and the above results can be explained by this model.

Capacitive coupling of line coded and DC-balanced digital signals is often used to eliminate steady bias current flow between the systems or components in various communication systems. A multi-layer ceramic chip capacitor is promising for the capacitor of very broadband signal coupling because of its high frequency characteristics expected from the downsizing of the chip recent years. The lower limit of the coupling bandwidth is determined by the capacitance while the higher limit is affected by the parasitic inductance associated with the chip structure. In this paper, we investigate the coupling characteristics up to millimeter wave frequencies by the measurement and simulations. A phenomenon has been found in which the change in the current distribution in the chip structure occur at high frequencies and the coupling characteristics are improved compared to the prediction based on the conventional equivalent circuit model. A new equivalent circuit model of chip capacitor that can express the effect of the improvement has been proposed.

For low-density parity-check (LDPC) codes, the penalized decoding method based on the alternating direction method of multipliers (ADMM) can improve the decoding performance at low signal-to-noise ratios and also has low decoding complexity. There are three effective methods that could increase the ADMM penalized decoding speed, which are reducing the number of Euclidean projections in ADMM penalized decoding, designing an effective penalty function and selecting an appropriate layered scheduling strategy for message transmission. In order to further increase the ADMM penalized decoding speed, through reducing the number of Euclidean projections and using the vertical layered scheduling strategy, this paper designs a fast converging ADMM penalized decoding method based on the improved penalty function. Simulation results show that the proposed method not only improves the decoding performance but also reduces the average number of iterations and the average decoding time.

Reference current used in sense amplifiers is a crucial factor in a single-end read manner for emerging memories. Dummy cell average read scheme uses multiple pairs of dummy cells inside the array to generate an accurate reference current for data sensing. The previous research adopts current mirror sense amplifier (CMSA) which is compatible with the dummy cell average read scheme. However, clamped bit-line sense amplifier (CBLSA) has higher sensing speed and lower power consumption compared with CMSA. Therefore, applying CBLSA to dummy cell average read scheme is expected to enhance the performance. This paper reveals that direct combination of CBLSA and dummy cell average read scheme leads to sense margin degradation. In order to solve this problem, a new array design is proposed to make CBLSA compatible with dummy cell average read scheme. Current mirror structure is employed to prevent CBLSA from being short-circuited directly. The simulation result shows that the minimum sensible tunnel magnetoresistance ratio (TMRR) can be extended from 14.3% down to 1%. The access speed of the proposed sensing scheme is less than 2 ns when TMRR is 70% or larger, which is about twice higher than the previous research. And this circuit design just consumes half of the energy in one read cycle compared with the previous research. In the proposed array architecture, all the dummy cells can be always short-circuited in totally isolated area by low-resistance metal wiring instead of using controlling transistors. This structure is able to contribute to increasing the dummy cell averaging effect. Besides, the array-level simulation validates that the array design is accessible to every data cell. This design is generally applicable to any kinds of resistance-variable emerging memories including STT-MRAM.

Vision systems are widely adopted in industrial fields for monitoring and automation. As a typical example, industrial vision systems are extensively implemented in vibrator parts feeder to ensure orientations of parts for assembling are aligned and disqualified parts are eliminated. An efficient parts orientation recognition and counting method is thus critical to adopt. In this paper, an integrated method for fast parts counting and orientation recognition using industrial vision systems is proposed. Original 2D spatial image signal of parts is decomposed to 1D signal with its temporal variance, thus efficient recognition and counting is achievable, feeding speed of each parts is further leveraged to elaborate counting in an adaptive way. Experiments on parts of different types are conducted, the experimental results revealed that our proposed method is both more efficient and accurate compared to other relevant methods.

We propose a non-photorealistic rendering method for generating edge-preserving bubble images from gray-scale photographic images. Bubble images are non-photorealistic images embedded in many bubbles, and edge-preserving bubble images are bubble images where edges in photographic images are preserved. The proposed method is executed by an iterative processing using absolute difference in window. The proposed method has features that processing is simple and fast. To validate the effectiveness of the proposed method, experiments using various photographic images are conducted. Results show that the proposed method can generate edge-preserving bubble images by preserving the edges of photographic images and the processing speed is high.

Information and communication technologies have improved the quality of intelligent transportation systems (ITS). By estimating from cellular floating vehicle data (CFVD) is more cost-effective, and easier to acquire than traditional ways. This study proposes a cell probe (CP)-based method to analyse the cellular network signals (e.g., call arrival, handoff, and location update), and regression models are trained for vehicle speed estimation. In experiments, this study compares the practical traffic information of vehicle detector (VD) with the estimated traffic information by the proposed methods. The experiment results show that the accuracy of vehicle speed estimation by CP-based method is 97.63%. Therefore, the CP-based method can be used to estimate vehicle speed from CFVD for ITS.