This paper presents a comprehensive investigation of three optical wavelength-division multiplexed (WDM) mesh network protection approaches, namely minimal cost, single link basis and disjoint path approaches. The operation of each approach is described and their performances are extensively evaluated and compared. Key aspects that are taken into the consideration and comparison of the designs include a spare capacity requirement, ease of operation and practical feasibility. A mathematical model based on integer linear programming is introduced to obtain a lower bound on the spare capacity requirement for full protection against all single link failures. Two heuristic algorithms have also been developed to perform wavelength resource allocation under both normal and failure conditions for both systems with and without wavelength conversion capability. It is shown that the minimal cost approach can accomplish the lowest extra cost requirement for protection, but this approach is considered not appropriate for practical applications due to complicated restoration and management. The single link basis scheme is on the other hand more practical and very cost efficient. For the disjoint path technique, the cost for spare capacity is generally slightly greater than that of the single link basis scheme. Its main advantages lie in the simple re-configuration and inherent protection against node failure for in-transit traffic. Finally, a new framework for obtaining a good spare capacity cost estimate of a mesh restorable network is presented.

In this paper, a multi-coded variable spreading gain (MC-VSG) CDMA system employing a binary transmission of MC signals by introducing a level clipper, termed MC-VSG BNet system, is proposed for a possible candidate of wireless personal area network (WPAN) and 3 G cellular applications. With an emphasis on the MC-VSG BNet physical layer and the system performance, we address the concise specification of the MC-VSG BNet system including the spreading code, level clipping, modulation, coding, and frame format. Especially, we focus on the level clipping of multi-level MC signals for both power- and cost-efficient implementation and the VSG code design fir high-rate transmissions. From the receiver performance based on simulation results, in addition to simple receiver structure, an acceptable performance degradation of the MC-VSG BNet system over the existing DS/CDMA system is observed, while guaranteeing an high bit rate transmission.

An n-detection testing for stuck-at faults can be used not only for delay fault testing but also for detection of unmodeled faults. We have developed a hybrid BIST circuit; that is, a method consisting of a shift register with partial rotation and a procedure that selects test vectors from ATPG ones. This testing method can perform at-speed testing with high stuck-at fault coverage. During the at-speed testing, a subset of the ATPG vectors is input by using a low-speed tester. Computer simulations on ISCAS'85, ISCAS'89, and ITC'99 circuits are conducted for n = 1, 2, 3, 5, 10, and 15. The simulation results show that the amount of test vectors can be reduced to ranging from 52.3% to 0.9% in comparison with that of the ATPG vectors. As a result, the proposed method can reduce the cost of at-speed testing.

This paper deals with formal verification of high-level designs, in particular, symbolic comparison of register-transfer-level descriptions and behavioral descriptions. We use state machines extended by quantifier-free first-order logic with equality, as models of those descriptions. We cannot adopt the classical notion of equivalence for state machines, because the signals in the corresponding outputs of such two descriptions do not change in the same way. This paper defines a new notion of consistency based on signal-transitions of the corresponding outputs, and proposes an algorithm for checking consistency of those descriptions, up to a limited number of steps from initial states. As an example of high-level designs, we take a simple hardware/software codesign. A C program for digital signal processing called PARCOR filter was compared with its corresponding design given as a register-transfer-level description, which is composed of a VLIW architecture and assembly code. Since this example terminates within approximately 4500 steps, symbolic exploration of a finite number of steps is sufficient to verify the descriptions. Our prototype verifier succeeded in the verification of this example in 31 minutes.

One of the reasons of slow convergence in Backpropagation learning is the diminishing value of the derivative of the commonly used activation functions as the nodes approach extreme values, namely, 0 or 1. In this letter, we propose arctangent activation function to accelerate learning speed. Simulation results indicate considerable improvement in convergence performance.

Metal particulate tape is one of the most advanced tape media to offer excellent performance at high recording densities. An accurate micromagnetic model of the metal particulate tape has been developed to analyze the magnetic properties of MP tapes. Both particle size distributions and orientation distribution are included in the model, and the magnetostatic interactions among particles are accurately calculated with the shape of ellipsoids. A partial mean field approximation applied in the calculation is proved to be effective by M-H loop analysis.

In recent years, the domino logic has received much attention as a design technique of high-speed circuits. However, in the case of standard domino logic, only non-inverting functions are allowed. Then, the clock-delayed (CD) domino logic that provides any logic function is proposed in order to overcome such domino's drawback. In addition, domino circuits are more sensitive to circuit noise compared with static CMOS circuits. In particular, crosstalk causes critical problems. Therefore, we focus our attention on crosstalk faults in CD domino circuits. However, in CD domino circuits, there are faults that don't propagate faulty values to any primary output even though crosstalk pulses are generated. Then, we remove such faults from the target fault list by considering structures of CD domino circuits, and perform a fault simulation for the reduced target fault list using two kinds of fault simulation method together. We realize CD domino circuits in VHDL and perform the proposed fault simulation for the combinational part of some benchmark circuits of ISCAS'89 on a VHDL simulator. Fault coverage for random vectors was obtained for s27 to s1494 under the limitation of simulation time.

The increase of test time of embedded DRAMs (e-DRAM) is one of the key issues of System-on-chip (SOC) device test. This paper proposes to put the repair analysis function on chip as Built In Self Repair (BISR). BISR is performed at 166 MHz as at-speed of e-DRAM with using low cost automatic test equipment (ATE). The area of the BISR is 1.7 mm2. Using error storage table form contributes to realize small area penalty of repair analysis function. e-DRAM function test time by BISR was about 20% less than the conventional method at wafer level testing. Moreover, representative samples are produced to confirm repair analysis ability. The results show that all of the samples are actually repaired by repair information generated by BISR.

This paper presents a practical fault model for delay testing, called a multiple-threshold gate-delay fault model, to obtain high quality tests that guarantee the detection of delay faults for various extra-delays. Fault efficiencies for multiple thresholds of the extra-delay are introduced as a coverage metric that describes the quality of tests. Our approach guarantees that each gate-delay fault is tested on the path that is almost the longest one passing through the faulty line by using two-pattern tests with pattern-independent timing. We present the procedures of the path selection, fault simulation, and the test generation, where the path-status graph technique is used as not to rely on the enumeration of paths. Experimental results for benchmark circuits demonstrate that the proposed metric gives useful information that transition fault efficiency cannot, and that the proposed test generation can achieve high fault efficiencies for multiple-threshold gate-delay faults.

A dynamic pre-allocated connection (DPC) scheme is proposed to support fast handoff and to effectively utilize wireline links in a multi-connection call environment. Handoff can be quickly executed in real-time with reduced connection overhead, since the proposed scheme uses pre-allocated switched virtual connections (PSVCs). This dynamic resource management scheme increases link utilization due to statistical multiplexing effects. A path-loop elimination algorithm can be applied to remove duplicate resource usages. The DPC scheme in an environment of multi-connection calls is analyzed to obtain three probabilities; 1) new multi-connection call blocking probability, 2) multi-connection handoff call blocking probability, and 3) fast handoff failure probability.

The electromagnetic wave scattering from ocean-like lossy dielectric random rough surfaces is numerically analyzed by using FVTD method. We have investigated the problem of low-grazing-angle (LGA) scattering in order to gain a better understanding of experimental data for the microwave backscattering from ocean-like surfaces. It is indicated that the FVTD results are in good agreement with the experimental data.

This paper proposes a design method of 2-D variable IIR digital filters with high frequency tuning accuracy. In the proposed method, a parallel complex allpass structure is used as the prototype structure of the 2-D variable digital filters in order to obtain low sensitivity characteristic. Because the proposed 2-D variable digital filter is composed of first-order complex allpass sections connected in parallel, the proposed variable digital filter possesses several advantages such as low sensitivity characteristic in the passband, simple stability monitoring and high parallelism. In order to improve the frequency tuning accuracy of the proposed variable digital filter, each first-order complex allpass section is substituted by a new first-order complex allpass section with low sensitivity characteristic. Moreover, the coefficient sensitivity analysis of a 2-D parallel complex allpass structure is presented. Numerical examples show that the proposed 2-D variable IIR digital filter has high tuning accuracy under the finite coefficient wordlength.

This paper addresses the single channel speech enhancement method which utilizes the mean value and variance of the logarithmic noise power spectra. An important issue for single channel speech enhancement algorithm is to determine the trade-off point for the spectral distortion and residual noise. Thus the accurate discrimination between speech spectral and noise components is required. The conventional methods determine the trade-off point using parameters obtained experimentally. As a result spectral discrimination is not adequate. And the enhanced speech is deteriorated by spectral distortion or residual noise. Therefore, a criteria to determine the point is necessary. The proposed method determines the trade-off point of spectral distortion and residual noise level by discrimination between speech spectral and noise components based on statistical criteria. The spectral discrimination is performed using hypothesis testing that utilizes means and variances of the logarithmic power spectra. The discriminated spectral components are divided into speech-dominant spectral components and noise-dominant ones. For the speech-dominant ones, spectral subtraction is performed to minimize the spectral distortion. For the noise-dominant ones, attenuation is performed to reduce the noise level. The performance of the method is confirmed in terms of waveform, spectrogram, noise reduction level and speech recognition task. As a result, the noise reduction level and speech recognition rate are improved so that the method reduces the musical noise effectively and improves the enhanced speech quality.

Face detection from cluttered images is very challenging due to the wide variety of faces and the complexity of image backgrounds. In this paper, we propose a neural network based approach for locating frontal views of human faces in cluttered images. We use a radial basis function network (RBFN) for separation of face and non-face patterns, and the complexity of RBFN is reduced by principal component analysis (PCA). The influence of the number of hidden units and the configuration of basis functions on the detection performance was investigated. To further improve the performance, we integrate the distance from feature subspace into the RBFN. The proposed method has achieved high detection rate and low false positive rate on testing a large number of images.

This paper proposes a channel monitor-based unequal error protection scheme using a dynamic OFDM subcarrier assignment technique for broadband video transmission systems in frequency selective fading environments. In the proposed system, to achieve stable regeneration of the received video, subcarriers with relatively high channel gain are assigned to the high priority data (HPD) in the MPEG data. To further guarantee a required transmission quality of the HPD, the proposed system also employs subcarrier transmission power control with delay profile information (DPI) feedback-type channel estimation technique. Computer simulation confirms that the proposed technique is effective in preventing quality degradation with about 20 dB lower transmission power than the conventional systems in frequency selective fading environments.

In this paper, the analysis, design and experimental results of active array applicator are presented. The injection-locking technique is used to alter the magnitude of the microwave sources so that the steering of near fields can be achieved. This technique can be applied for microwave hyperthermia cancer treatment to provide the large uniform temperature distribution. The complexity of the system can be reduced by using this technique. The study shows that the temperature distribution can be controlled by varying the modulation index, modulating frequency and initial phase of modulating signal. The temperature distribution is also affected by applicator configuration, spacing between applicators, and heating time. The Spectral Domain approach is used to analyze the near field and then the near field data are used to find the temperature distribution by using the Finite Difference method. The study is carried out at frequency of 2,450 MHz. This design is useful for implementation of the low cost steerable applicator.

We present a method to track and recognize shape-changing hand gestures simultaneously. The switching linear model using active contour model well corresponds to temporal shapes and motions of hands. However, inference in the switching linear model is computationally intractable, and therefore the learning process cannot be performed via the exact EM (Expectation Maximization) algorithm. Thus, we present an approximate EM algorithm using a collapsing method in which some Gaussians are merged into a single Gaussian. Tracking is performed through the forward algorithm based on Kalman filtering and the collapsing method. We also present a regularized smoothing, which plays a role of reducing jump changes between the training sequences of shape vectors representing complex-variable hand shapes. The recognition process is performed by the selection of a model with the maximum likelihood from some trained models while tracking is being performed. Experiments for several shape-changing hand gestures are demonstrated.

This paper presents a test vector modification method for reducing average power dissipation during test application for a full-scan circuit. The method first identifies a set of don't care (X) inputs of given test vectors, to which either logic value 0 or 1 can be assigned without losing fault coverage. Then, the method reassigns logic values to the X inputs so as to decrease switching activity of the circuit during scan shifting. Experimental results for benchmark circuits show the proposed method could decrease switching activity of a given test set to 45% of the original test sets in average.

Interpolation surfaces, such as Bezier or B-spline surface, are usually used for representing smooth man-made objects and provide an excellent ability to control the shape of a surface by intuitively moving control points. In contrast, the fractal technique is used for creating various complex shapes, mainly of natural objects, that have self-similarity using simple procedures. We have proposed the "wrinkly surface (WR surface)" for combining the advantages of interpolation surfaces and fractals. In this paper, we propose the expansion of the construction scheme of the WR surface to irregular meshes. Control points of a WR surface are interpolated using the "Iterated Shuffle Transformation (IST)." Therefore, in order to achieve the expansion, we first generalize the IST on code spaces, and then propose multi-dimensional IST defined on geometric spaces. By creating various shape model examples, we demonstrate the usefulness of the WR surface as a modeling tool.

This paper presents a multiple-valued logic-in-memory circuit with real-time programmability. The basic component, in which a dynamic storage function and a multiple-valued threshold function are merged, is implemented compactly by using charge storage and capacitive coupling with a DRAM-cell-based circuit structure under a 0.8-µm CMOS technology. The pass-transistor network using these basic components makes it possible to realize any multiple-valued-inputs binary-outputs logic circuits compactly. As a typical example, a fully parallel multiple-valued magnitude comparator is also implemented by using the proposed DRAM-cell-based pass-transistor network. Its execution time and power dissipation are reduced to about 11 percent and 29 percent, respectively, in comparison with those of a corresponding binary implementation. A prototype chip is also fabricated to confirm the basic operation of the proposed DRAM-cell-based logic-in-memory circuit.