In this letter, sampling and quantizer design for the Gaussian detection problem are considered. A constraint on the transmission rate from the remote sensor to the optimal discrete detector is assumed. The trade-off between sampling rate and the number of quantization levels is studied and illustrated by means of an example.

The mobile computing system is a set of functions on a distributed environment organized to support mobile hosts. In this environment, mobile hosts should be able to move without any constraints and should remain connected to the network even while moving. Also, they should be able to get necessary information regardless of their current location and time. Distributed mutual exclusion methods for supporting distributed algorithms have hitherto been designed for networks only with static hosts. However, with the emergence of mobile computing environments, a new distributed mutual exclusion method needs to be developed for integrating mobile hosts with underlying distributed systems. In the sense, many issues that should be considered stem from three essential properties of mobile computing system such as wireless communication, portability, and mobility. Thus far, distributed mutual exclusion methods for mobile computing environments were designed based on a token ring structure, which has the drawback of requiring high costs in order to locate mobile hosts. In this paper, we propose not only a distributed mutual exclusion method that can reduce such costs by structuring the entire system as a tree-based logical structure but also recovery schemes that can be applied when a node failure occurs. Finally, we evaluate the operation costs for the mutual exclusion scheme and the recovery scheme.

Existing byte error control codes require too many check bits if applied to a memory system that uses recent semiconductor memory chips with wide I/O data such as 16 or 32 bits, i.e., b=16 or 32. On the other hand, semiconductor memory chips are highly vulnerable to random double bit within a memory chip errors when they are used in some applications, such as satellite memory systems. Under this situation, it becomes necessary to design suitable new codes with double bit within a chip error correcting capability for computer memory systems. This correspondence proposes a class of codes called Double bit within a block Error Correcting - Single b-bit byte Error Correcting ((DEC)B-SbEC) codes where block and byte correspond to memory chip and memory sub-array data outputs, respectively. The proposed codes provide protection from both random double bit errors and single sub-array data faults. For most of the practical cases, the (DEC)B-SbEC codes presented in this correspondence have the capability of accommodating the check bits in a single dedicated memory chip.

The stateless-based cache invalidation schemes for wireless environments can be categorized into either asynchronous or synchronous cache invalidation according to the broadcasting way of invalidation report. However, if the asynchronous cache invalidation scheme attempts to support local processing of read-only transaction, a critical problem may occur; the asynchronous invalidation reports provide no guarantee of waiting time for mobile transactions requesting commit. To solve this problem, the server in our approaches broadcasts two kind of messages, asynchronous invalidation report to reduce transaction latency and periodic guide message to avoid the uncertainty of waiting time for the next invalidation report. This paper presents a simulation-based analysis on the performance of the suggesting algorithms. The simulation experiments show that the local processing algorithms of read-only transaction based on asynchronous cache invalidation scheme get better response time than the algorithm based on synchronous cache invalidation scheme.

We consider to design approximation algorithms for the survivable network design problem in hypergraphs (SNDPHG) based on algorithms developed for the survivable network design problem in graphs (SNDP) or the element connectivity problem in graphs (ECP). Given an instance of the SNDPHG, by replacing each hyperedge e={v1,,vk} with a new vertex we and k edges {we, v1},, {we, vk}, we define an SNDP or ECP in the resulting graph. We show that by approximately solving the SNDP or ECP defined in this way, several approximation algorithms for the SNDPHG can be obtained. One of our results is a dmax+-approximation algorithm for the SNDPHG with dmax 3, where dmax (resp. dmax+) is the maximum degree of hyperedges (resp. hyperedges with positive cost). Another is a dmax+(rmax)-approximation algorithm for the SNDPHG, where (i)=j=1i(1/j) is the harmonic function and rmax is the maximum connectivity requirement.

A 1-V 2-GHz receiver that exhibits an image rejection of 49 dB is described. It consists of a low-noise amplifier, a quadrature mixer and on-chip polyphase filters, and was fabricated by 0.2-µm fully depleted CMOS/SIMOX technology. The quadrature mixer employs an LC-tuned folded structure with a common RF input for I and Q channels. This enables 1-V operation, suppresses phase errors in LO signals, and improves the image-rejection performance by about 15-dB compared to a conventional quadrature architecture. The current source of the single-to-balance converter at the mixer input consists of a transistor and an LC tank in a cascode configuration. This enhances its output impedance and improves its common-mode-rejection ratio (CMRR) and the IIP2 characteristics of the receiver. The chip consumes 12 mW with 1-V power supply. The receiver provides an NF of 10 dB with an IIP3 of -15.8 dBm and IIP2 of 12.3 dBm.

The analog inverter for realization of the NOT function is the indispensable circuit element in the voltage-mode analog and digital signal processing. In this paper, we propose a novel analog inverter composed of only two neuron-MOS transistors. The analog inverter has the weighted negative feedback mechanism to operate both of neuron-MOS transistors under the saturation region in all input ranges. In verification using HSPICE simulations, the analog inverter performs the high linearity with errors of approximately 40 [mV] in all input ranges, particularly errors of less than 19 [mV] in more than 90% of input ranges. And, the maximum power consumption of the analog inverter is less than 1.5 [µW] although a peak of a standard CMOS inverter is around 30 [µW] under the supply voltage of 3.0 [V]. These good stability and results are produced by the negative feedback. Furthermore, fabrication costs of the analog inverters can be kept at the minimum because neuron-MOS transistors can be actualized in a conventional CMOS process without any additional process. For applications of the analog inverter, the voltage comparator with high noise margins is designed and is applied to the two-input MAX and the two-input MIN circuits in the voltage-mode. The MAX and the MIN circuits for realization of the MAX and the MIN functions, respectively, can be composed of total ten transistors each. They also perform well in verifications. On the basis of the proposed circuits, almost all of voltage-mode multi-valued logic circuits with high-performance can be realized like present binary logic systems. And, the proposed circuits can give full play to the high linearity and advantages for the arbitrary transformation of signal forms in the analog signal processing such as the fuzzy control.

A fully on-chip active guard band circuit is proposed. The proposed circuit is mainly composed of current mirrors and based on a DC bias technique. HSPICE simulations and experiment results confirm the validity of the proposed active guard band circuit.

An embedded processor core using split branch architecture has been developed. This processor core targets 400 MHz using 0.18 µm technology, and its higher frequency needs deeper pipeline than the conventional processor. To solve the increasing branch penalty problem caused by a deeper pipeline, this processor takes an active preload mechanism to preload the target instructions to internal buffers in order to hide the instruction cache latency. The processor also uses multiple instruction buffers to reduce branch penalty cycles of branch misprediction. The performance estimation result shows that about 70% of branch overhead cycles can be reduced from the conventional implementation. The area for this branch mechanism consumes only 1% of the total core, which is smaller than the conventional branch target buffer (BTB) scheme, and helps to achieve low power and low cost.

In this paper, we discuss an IF image rejection system with variable bandwidth and center frequency. The system is consists of a pair of frequency mixers multiplied by the complex sinusoid and a complex analog filter. By employing the complex leapfrog structure using OTA-C configuration and the frequency transformation from the normalized LPF, the proposed system is capable of variable bandwidth and center frequency characteristics. SPICE simulations result more than 43 [dB] image rejection is achieved for 6 [kHz] and 12 [kHz] bandwidths at 50 [kHz] IF.

The backward direction Soft Output Viterbi Algorithm (a backward SOVA) is compared with the conventional SOVA (a forward SOVA) in turbo code decoding. We find noticeable performance improvement for the backward SOVA when it is not terminated, which turns out to be due to a smaller reliability value, indicating that the termination conditions of the turbo encoder strongly affect the performance of the backward SOVA decoder. We also propose a hardware efficient serially mixed SOVA decoder composed of a forward SOVA decoder and a backward SOVA decoder. Simulation results show that the proposed serially mixed SOVA decoder has a 0.2 dB coding gain at 2.0 dB Eb/No over the forward SOVA for a typical turbo code example.

Besides single byte errors which are caused by single chip failures, semiconductor memories used in some applications, such as satellite memory systems, are highly vulnerable to random double bit errors. It is therefore necessary to design Double bit Error Correcting--Single b-bit byte Error Correcting (DEC-SbEC) codes which correct both random double bit errors and single b-bit byte errors. This correspondence proposes a class of generic DEC-SbEC codes that are applicable to computer memory systems using recent high density DRAM chips with wide I/O data, such as, 8, 16 or 32 bits per chip. The proposed DEC-S8EC codes are suitable for memory systems using DRAM chips with 8-bit I/O data, and require 24 check bits for practical information lengths such as 64 and 128 bits.

In order to navigate a mobile robot or an autonomous vehicle in indoor environment, which includes several kinds of obstacles such as walls, furniture, and humans, the distance between the mobile robot and the obstacles have to be determined. These obstacles can be considered as walls with complicated edges. This paper proposes a mobile-robot-navigation method by using the polar coordinate transformation from an omnidirectional image. The omnidirectional image is obtained from a hyperboloidal mirror, which has the prominent feature in sensing the surrounding image at the same time. When the wall image from the camera is transformed by the transformation, the straight lines between the wall and the floor appear in the curve line after transformation. The peak point represents the distance and the direction between the robot and the wall. In addition, the wall types can be classified by the pattern and number of peak points. They are one side wall, corridor and corner. To navigate the mobile robot, in this paper, it starts with comparing a peak point obtained from the real image with the reference point determined by designed distance and direction. If there is a difference between the two points, the system will compute appropriate wheel angle to adjust the distance and direction against the wall by keeping the peak point in the same position as the reference point. The experiments are performed on the prototype mobile robot. The results show that for the determining distance from the robot to the wall between 70-290 cm, the average error is 6.23 percent. For three types of the wall classification, this method can correctly classify 86.67 percent of 15 image samples. In the robot movement alongside the wall, the system approximately consumes the 3 frame/s processing time at 10 cm/s motion speed. The mobile robot can maintain its motion alongside the wall with the average error 12 cm from reference distance.

This study attempts to demonstrate that activated leukocytes are involved in vascular shut down effect (VSD) in photodynamic therapy (PDT). Hydrogen peroxide (H2O2), a reactive oxygen specie (ROS) that is found in monocytes, was visualized under a confocal laser scanning microscope, and ROS formation was quantified by fluorescence image analysis. The fluorescence intensity was expressed as a gray level graded from 0 to 255. Only the fluorescence derived from monocytes that had ZnCP-III incorporated and were irradiated with an HeNe laser caused increases in the fluorescence distribution over time, while no change of distribution was observed in three other conditions (only Zn CP-III added, only HeNe laser irradiation, or non-treated). The result indicates that the photochemical reaction induced by excitation of a photosensitizer, and ROS was derived from the reaction-stimulated monocytes. The activated monocytes generated ROS themselves and H2O2 was visualized by the DCFH fluorescence method. In conclusion, the result clearly shows that activated monocytes are involved in the VSD effect.

When a randomized algorithm elects a leader on anonymous networks, initial information (which is called in general initial condition in this paper) of some sort is always needed. In this paper, we study common properties of initial conditions that enable a randomized algorithm to elect a leader. In the previous papers, the author introduced the notion of transformation between initial conditions using distributed algorithms. By using this notion of transformation, we investigate the property of initial conditions for the leader election. We define that an initial condition C is p(N)-complete if there exists some randomized algorithm that elects a leader with probability p(N) on any size N network satisfying C. We show that we can divide p(N)-completeness into four types as follows. 1. p(N)=1: For any 1-complete initial conditions, there exists a deterministic distributed algorithm that can compute the size of the network for any initial information satisfying the initial condition. 2. inf p(N) >0: For any p(N)-complete initial conditions with inf p(N) >0, there exists a deterministic distributed algorithm that can compute an upper-bound for the size of the network for any initial information satisfying the initial condition. 3. inf p(N) converges to 0: The set of p(N)-complete initial conditions varies depending on the decrease rate of p(N). 4. p(N) decreases exponentially: Any initial condition is regarded as p(N)-complete.

This paper presents a method for detection of calcification, which is an important early sign of breast cancer in mammograms. Since information of calcifications is located in inhomogeneous background and noises, it is hard to be detected. This method uses wavelet packet transform (WPT) for elimination of the background image related to low frequency components. However, very high frequency signals of noises exist with the calcifications and make it hard to suppress them. Since calcification location can be represented as vertical, horizontal, and diagonal edges in time-frequency domain, the edges in spatial domain can be utilized as a filter for noise suppression. Then the image from inverse transform will contain only required information. A free-response operating characteristic (FROC) curve is used to evaluate a performance of proposed method by applying it to thirty images of calcifications. The results show 82.19 percent true positive detection rate at the cost of 6.73 false positive per image.

We applied control theory to nerve-muscle in order to model and systematize the muscle system. The association between nerve stimulation frequencies and electromyogram (EMG) amplitude was studied in rat nerve-muscle under normal and hypokalemic conditions. From these results, we modeled the nerve-muscle and simulated frequency response from the nerve-muscle system which can be expressed as a closed loop transfer function.

For several years, more and more people are joining the Internet and various kind of packets (so called transaction-, block-, and stream-types) have been transmitted in the same network, so that poor network conditions cause loss of the stream-type data packets, such as voices, which request smaller transmission delay time than others. We consider a switching node (router) in a network as an N-series M/G/1-type queueing model and have mainly evaluated the fluctuation of packet delay time and end-to-end delay time, using the two moments matching method with initial value, then define the delay jitter D of a network which consists of jointed N switching nodes. It is clarified that this network is not suitable for voice packets transmission media without measures.

The provisioning of QoS in the Internet is gaining an increasing attention, thus the importance of methods capable of estimating the bandwidth requirement of traffic flows is constantly growing. This information can be used for a wide range of purposes. Admission control, QoS routing and load sharing all need the same basic information in order to be able to make decisions. This paper describes a number of methods that can be used to arrive at precise estimates of the bandwidth requirement focusing on those that are based on the theory of large deviations. A methodology is presented that allows the reformulation of earlier solutions based on the estimation of some form of an overflow probability so that their output becomes a bandwidth-type quantity, the format preferred by Internet control applications. The methodology provides two tracks for the conversion: an indirect method that encapsulates the overflow probability-type approach as an embedded calculation and a direct method that immediately results in the estimate of the bandwidth requirement. The paper introduces a novel method for the direct computation of the bandwidth requirement of Internet traffic flows using the many sources asymptotic regime of the large deviation theory. The direct bandwidth estimator method reduces the computational complexity of the calculations, since it results directly in the bandwidth requirement, allowing the omission of the frequent and costly computation of the buffer overflow probability. The savings arising from the reduction in computational complexity are demonstrated in a numerical example.

The function of a message authentication code (MAC) is to verify the validity of a whole message. The disadvantage of usual MACs is that a receiver can not check its validity until the receipt of a message is finished. Hence, usual MACs are not suitable for verifying a large amount of data such as video and audio (called stream). In this letter, we propose a MAC such that the validity of a stream can be consecutively verified without waiting for the end of the reception. In addition, we show its implementations: one is based on practical hash functions, and the other is based on universal hash functions.