A 150 GHz fundamental oscillator employing an inter-stage matching network based on a transmission line is presented in this letter. The proposed oscillator consists of a two-stage common-emitter amplifier loop, whose inter-stage connections are optimized to meet the oscillation condition. The oscillator is designed in a 130-nm SiGe BiCMOS process that offers fT and fMAX of 350 GHz and 450 GHz. According to simulation results, an output power of 3.17 dBm is achieved at 147.6 GHz with phase noise of -115 dBc/Hz at 10 MHz offset and figure-of-merit (FoM) of -180 dBc/Hz.

Since 2020, the service of the 5th generation (5G) mobile phone has been started. In order to increase the transmission speed in 5G mobile phones, the multi-level of the modulated signal is advanced, and for that, the power amplifier (PA) high linearity is required even at low output power. In accordance with this, the review of the linearization technology of a PA has become important. As a performance index of the distortion of the PA, the output power dependence of the gain and phase, the AM (Amplitude Modulation)-AM/PM (Phase Modulation) characteristic is well known. There has been a lot of consideration for the AM-AM/PM characteristics of PA. The AM-AM/PM characteristics are affected by both source and load impedances. In this paper, a single-stage HBT (Hetero-junction Bipolar Transistor) PA is described by a simple linear equivalent circuit with multiple parameter sets. Each parameter set is defined according to the PA output power level. With this simple model, we investigated the change of AM-AM/PM characteristics when the reactance parts of source and load impedances was changed. It has become clear that change in the AM-AM/PM characteristics of the PA when the parameters were changed was mainly due to the change in the AM-AM/PM characteristics at the base node.

The paper presents the analysis, design and performance of PCB (Printed Circuit Board)-based cross-coupled differential VCOs using a novel LC-tank. As compared with the conventional LC-tank, a novel LC-tank is comprised of only chip inductors and thus has an advantage in providing a higher cutoff frequency. This feature attributes to the use of the parasitic elements of the chip inductors and capacitors. The cutoff frequencies were compared for both LC-tanks by calculation, simulation and measurement. Then the traditional cross-coupled differential oscillators having both LC-tanks were designed, fabricated and performed by using 0.35µm SiGe HBTs and 1005-type chip devices. The implemented oscillator using a novel LC-tank has shown a 0.12GHz higher oscillation frequency, while phase noise characteristics were almost the same. In addition, the cross-coupled differential oscillator utilizes a series RL circuit in order to suppress the concurrent oscillations. The implemented cross-coupled differential VCO employing Si varactor diodes with a capacitance ratio of 2.5 to 1 has achieved a tuning frequency of 0.92 to 1.28GHz, an output power greater than -13.5dBm, a consumed power less than 8.7mW and a phase noise at 100kHz offset in a range from -104 to -100dBc/Hz.

This paper describes the design and measurements of two-gain-mode MMIC power amplifier modules (PAMs) for Band 1 and Band 5 WCDMA data communications. The PAMs are based on the two-stage single-chain amplifier topology with an L-shaped FET step attenuator (ATT) placed at the interstage, featuring not only high-efficiency operation but also both a small phase discontinuity and a small input return loss variation between the two gain modes: a high-gain mode (0-dB thru state for the ATT) and a low-gain mode (14-dB attenuation state for the ATT). The PAMs are assembled on a 3 mm × 3 mm FR-4 laminate together with several surface mount devices, and a high-directivity, 20-dB bilayer-type directional coupler is integrated on the laminate for accurate forward-power monitoring even under a 2.5:1-VSWR load mismatching condition. To validate the design and analysis for the PAMs using the L-shaped ATT, two PAM products — a Band 1 PAM and a Band 5 PAM — were fabricated using our in-house GaAs-BiFET process. The main RF measurements under the condition of a WCDMA (R99) modulated signal and a 3.4-V supply voltage are as follows. The Band 1 PAM can deliver a power-added efficiency (PAE) as high as 46% at an output power (Pout) of 28.25 dBm while maintaining a ±5-MHz-offset adjacent channel power ratio (ACLR1) of approximately -40 dBc or less and a small phase discontinuity of less than 5°. The Band 5 PAM can also deliver a high PAE of 46% at the same Pout and ACLR1 levels with small phase discontinuity of less than 4°. This small discontinuity is due to the phase-shift compensation capacitance embedded in the ATT. The measured input return loss is well maintained at better than 10 dB at the two modes. In addition, careful coupler design achieves a small detection error of less than 0.5 dB even under a 2.5:1-VSWR load mismatching condition.

This paper describes, for the first time, an experimental study on the layout design considerations of GaAs HBT MMIC switchable-amplifier-chain-based power amplifiers (SWPAs) for CDMA handsets. The transient response of the quiescent current and output power (Pout) in GaAs HBT power amplifiers that consist of a main chain and a sub-chain is often affected by a thermal coupling between power stages and their bias circuits in the same chain or a thermal coupling between power stages and/or their bias circuits in different chains. In particular, excessively strong thermal coupling inside the MMIC SWPA causes failure in 3GPP-compliant inner loop power control tests. An experimental study reveals that both the preheating in the main/sub-chains and appropriate thermal coupling inside the main chain are very effective in reducing the turn-on delay for the two-parallel-amplifier-chain topology; for example, i) the sub-power stage is arranged near the main power stage, ii) the sub-driver stage is placed near the main driver stage and iii) the main driver bias circuit is placed near the main power stage and the sub-power stage. The SWPA operating in Band 9 (1749.9 to 1784.9 MHz), which was designed and fabricated from the foregoing considerations, shows a remarkable improvement in the Pout turn-on delay: a reduced power level error of 0.74 dB from turn-off to turn-on in the sub-amplifier chain and a reduced power level error of over 0.30 dB from turn-off to turn-on in the main amplifier chain. The main RF power measurements conducted with a 3.4-V supply voltage and a Band 9 WCDMA HSDPA modulated signal are as follows. The SWPA delivers a Pout of 28.5 dBm, a power gain (Gp) of 28 dB, and a PAE of 39% while restricting the ACLR1 to less than -40 dBc in the main amplifier chain. In the sub-amplifier chain, 17 dBm of Pout, 23.5 dB of Gp, and 27% of PAE are obtained at the same ACLR1 level.

This paper describes, for the first time, the circuit design considerations and measurements of core building blocks that support a 1.9-GHz-band (Band I) BiFET MMIC three-power-mode power amplifier (PA) for WCDMA handset applications. The blocks are a reference voltage (Vref) generator, a control logic circuit, and ESD protection circuits. Our proposed Vref-generator, based on a current-mirror topology, can successfully suppress Vref variation against threshold voltage (Vth) dispersion in the FET as well as current gain dispersion in the HBT. On-wafer measurements over several wafer lots show that the standard deviation of Vref is as small as 18 mV over a Vth dispersion range from -0.6 V to -1.0 V. As a result, the measured quiescent current dispersion in the HPM is also suppressed to less than 5.4 mA, despite the fact that the average quiescent current is relatively high, at 81.3 mA. Several simulations reveal that small decoupling capacitances of approximately 1 pF added to the gate control lines of RF switch FETs ensure stable operation of the control logic even if an undesired RF coupling is present between an RF signal path and the gate lines. An empirical and useful design approach for ESD protection using HBT base-collector diodes allows easy and precise estimation of the HBM ESD robustness. With the above building blocks, a 3 mm × 3 mm PA was designed and fabricated by an in-house BiFET process. Measurements conducted under the conditions of a 3.4-V supply voltage and a 1.95-GHz WCDMA modulated signal are as follows. The PA delivers a 28.3-dBm output power (Pout), a 28.2-dB power gain (Gp), and 40% PAE while restricting the ACLR1 to less than -42 dBc in the HPM. In the MPM, 17.4 dBm of Pout, 15.9 dB of Gp, and 25.3% of PAE are obtained, while in the LPM, the PA delivers 7 dBm of Pout, 11.7 dB of Gp, and 13.9% of PAE. The HBM ESD robustness is 2 kV.

This paper describes the circuit design and measurement results of a new GaAs-HBT RF power detector proposed for use in WiMAX and wireless LAN transmitter applications. The detector, which is based on a simple current-mirror topology, occupies a small die area. It is, therefore, not only easy to implement together with a GaAs-HBT power amplifier, but can also offer approximately logarithmic (linear-in-dB) characteristics. Because it can also be driven with small voltage amplitudes, it is suitable for base-terminal monitoring at an HBT power stage. When the detector is used as a base-terminal power monitor, an appropriate base resistance added to the detection HBT effectively suppresses frequency dispersion of the detected voltage characteristics. Measurements of a prototype detector incorporated into a single-stage HBT power amplifier fabricated on the same die are as follows. The detector is capable of delivering a detected voltage of 0.35-2.5 V with a slope of less than 0.17 V/dB over a 4-to-24-dBm output power range at 3.5 GHz while drawing a current of less than 1.8 mA from a 2.85-V supply. While satisfying a log conformance error of less than 1 dB over an amplifier output power range from 4 dBm to 24 dBm, it can also suppress the detected power dispersion within 0.18 dB at approximately 15 dBm of output power over a 3.1-3.9-GHz-wide frequency range. This dispersion value is approximately one-tenth that of a conventional collector-terminal-monitor-type diode detector.

This paper describes 0.8-/1.5-GHz-band GaAs-HBT power amplifier modules with a newly designed analog bias control scheme. This scheme has two features. One is to achieve approximately linear quiescent current control using not a BiFET process but only the usual HBT process. The other is to help improve linearity under reduced supply voltage and lower quiescent current operation. The following two key techniques are incorporated into the bias scheme. The first is to employ two different kinds of bias circuits: emitter follower bias and current injection bias. The second is the unique current injection bias block, based on the successful combination of an input buffer with an emitter resistance load and a current mirror. These techniques allow quiescent current control that is almost proportional to an externally applied analog control voltage. To confirm the effectiveness of the scheme, 0.8-GHz-band and 1.5-GHz-band power amplifier modules were designed and fabricated using the usual HBT process. Measurements conducted under the conditions of a 3.4V supply voltage and an HSDPA WCDMA modulated signal are as follows. The 0.8-GHz-band amplifier can deliver a 28-dBm output power (Pout), a 28.4-dB power gain (Gp), and 42% PAE while restricting the ACLR to less than -40dBc. For the 1.5-GHz-band amplifier, 28dBm of Pout, 29dB of Gp, and 41% of PAE are obtained with the same ACLR levels. The measurements also confirm that the quiescent current for the second stage in the amplifiers is approximately linearly changed from 14mA to 58mA over a control voltage ranging from 1.1V to 2.2V. In addition, our measured DG.09-based current dissipation with both supply voltage and analog bias controls is as low as 16.9mA, showing that the analog bias control scheme enables an average current reduction of more than 20%, as compared to a conventional supply voltage and two-step quiescent current control.

This paper describes circuit design and measurement results of a newly proposed GaAs-HBT step-gain amplifier configuration and its application to a 3.3-3.6 GHz WiMAX power amplifier module for use in customer premises equipment. The step-gain amplifier implemented using only a usual HBT process is based on a current-mirror-based, base-collector diode switches and a passive attenuator core for the purpose of bypassing a power-gain stage. The stage allows an individual design approach in terms of gain and attenuation levels as well as large operating current reduction in the attenuation state. To confirm the effectiveness of the proposed step-gain amplifier, a prototype of the amplifier was designed and fabricated, and then a WiMAX power amplifier module was also designed and fabricated as an application example of the proposed configuration to an amplifier product. Measurements are as follows. For a 3.5-V power supply and a 3.5-GHz non-modulated signal, the step-gain amplifier delivers 23.7 dBm of 1-dB gain compressed output power and 10.7 dB of linear gain in the amplification state. In the attenuation state, the amplifier exhibits 21 dBm of 1-dB gain expanded input power, -9.7 dB of gain, and 15 mA of current dissipation while keeping the gain stage switched off and maintaining input and output return loss of less than -10 dB at a 3.5-GHz band. The WiMAX amplifier operating with a 5-V supply voltage and a 64-QAM modulated signal is capable of delivering a 28.5-dBm linear output power, a 37-39 dB gain, and 15% of PAE over a wide frequency range from 3.3 to 3.6 GHz in the high-gain state while keeping error vector magnitude as low as 2.5%. This amplifier, which incorporates the proposed step-gain configuration into its interstage, enables a 24-dB gain reduction and a 45-mA large quiescent current reduction in the low-gain state.

Boneh et al. proposed the new idea of pairing-based cryptography by using the composite order group instead of prime order group. Recently, many cryptographic schemes using pairings of composite order group were proposed. Miller's algorithm is used to compute pairings, and the time of computing the pairings depends on the cost of calculating the Miller loop. As a method of speeding up calculations of the pairings of prime order, the number of iterations of the Miller loop can be reduced by choosing a prime order of low Hamming weight. However, it is difficult to choose a particular composite order that can speed up the pairings of composite order. Kobayashi et al. proposed an efficient algorithm for computing Miller's algorithm by using a window method, called Window Miller's algorithm. We can compute scalar multiplication of points on elliptic curves by using a window hybrid binary-ternary form (w-HBTF). In this paper, we propose a Miller's algorithm that uses w-HBTF to compute Tate pairing efficiently. This algorithm needs a precomputation both of the points on an elliptic curve and rational functions. The proposed algorithm was implemented in Java on a PC and compared with Window Miller's Algorithm in terms of the time and memory needed to make their precomputed tables. We used the supersingular elliptic curve y2=x3+x with embedding degree 2 and a composite order of size of 2048-bit. We denote w as window width. The proposed algorithm with w=6=2·3 was about 12.9% faster than Window Miller's Algorithm with w=2 although the memory size of these algorithms is the same. Moreover, the proposed algorithm with w=162=2·34 was about 12.2% faster than Window Miller's algorithm with w=7.

A microwave power amplifier with independently biased InGaP/GaAs HBTs is proposed, and its superior performance is confirmed. Using harmonic balance simulation, the optimal bias conditions for an amplifier with two independently biased InGaP/GaAs HBTs were investigated with the aim of achieving high-efficiency low-distortion performance. A 1.9-GHz-band cascode power amplifier was designed and fabricated. Power efficiencies and third-order intermodulation distortions (IMD3) for the fabricated amplifier were estimated. The collector bias voltage of the first stage transistor mainly affects power-added efficiency (PAE). The base bias current of the first-stage HBT mainly affects IMD3 characteristics, and that of the second-stage HBT mainly affects PAE. The proposed amplifier shows superior performance when compared to a conventional cascode amplifier. The amplifier achieved a maximum PAE of 68.0% with an output power of 14.8dBm, and IMD3 better than -35dBc with a PAE of 25.1%, for a maximum output power of 10.25dBm at 1.9GHz. A PAE of more than 60% was achieved from 1.87 to 1.98GHz.

We fabricated low-jitter 2:1 multiplexer (MUX) and 1:2 demultiplexer (DEMUX) modules for bit error rate testers that can be used for research into ultra-high-bitrate communication subsystems and devices with bitrates of over 100 Gbit/s. The 1:2 DEMUX IC design took into consideration an IC layout allowing module pin placement for optimal utility. With regard to mounting, the 2:1 MUX and 1:2 DEMUX modules were constructed using transmission lines of grounded coplanar waveguide (G-CPW) configuration, which offers excellent high-frequency characteristics. These modules operated at 113 Gbit/s with a low root mean square jitter of 548 fs and 587 fs, respectively.

L-band SiGe HBT frequency-tunable differential amplifiers with dual-bandpass or dual-bandstop responses have been developed for the next generation adaptive and/or reconfigurable wireless radios. Varactor-loaded dual-band resonators comprised of series and parallel LC circuits are employed in the output circuit of differential amplifiers for realizing dual-bandpass responses as well as the series feedback circuit for dual-bandstop responses. The varactor-loaded series and parallel LC resonator can provide a wider frequency separation between dual-band frequencies than the stacked LC resonator. With the use of the varactor-loaded dual-band resonator in the design of the low-noise SiGe HBT differential amplifier with dual-bandpass responses, the lower-band frequency can be varied from 0.58 to 0.77 GHz with a fixed upper-band frequency of 1.54 GHz. Meanwhile, the upper-band frequency can be varied from 1.1 to 1.5 GHz for a fixed lower-band frequency of 0.57 GHz. The dual-band gain was 6.4 to 13.3 dB over the whole frequency band. In addition, with the use of the varactor-loaded dual-band resonator in the design of the low-noise differential amplifier with dual-bandstop responses, the lower bandstop frequency can be varied from 0.38 to 0.68 GHz with an upper bandstop frequency from 1.05 to 1.12 GHz. Meanwhile, the upper bandstop frequency can be varied from 0.69 to 1.02 GHz for a lower bandstop frequency of 0.38 GHz. The maximal dual-band rejection of gain was 14.4 dB. The varactor-loaded dual-band resonator presented in this paper is expected to greatly contribute to realizing the next generation adaptive and/or reconfigurable wireless transceivers.

This paper is a report on a high ESD breakdown-voltage InP HBT transimpedance amplifier IC for optical video distribution systems. To make ESD breakdown-voltage higher, we designed ESD protection circuits integrated in the TIA IC using base-collector/base-emitter diodes of InP HBTs and resistors. These components for ESD protection circuits have already existed in the employed InP HBT IC process, so no process modifications were needed. Furthermore, to meet requirements for use in optical video distribution systems, we studied circuit design techniques to obtain a good input-output linearity and a low-noise characteristic. Fabricated InP HBT TIA IC exhibited high human-body-model ESD breakdown voltages (±1000 V for power supply terminals, ±200 V for high-speed input/output terminals), good input-output linearity (less than 2.9-% duty-cycle-distortion), and low noise characteristic (10.7 pA/ averaged input-referred noise current density) with a -3-dB-down higher frequency of 6.9 GHz. To the best of our knowledge, this paper is the first literature describing InP ICs with high ESD-breakdown voltages.

This paper investigates the effects of n-type doping in the emitter-base heterojunction vicinity on the DC and high-frequency characteristics of InP/InGaAs heterojunction bipolar transistors (HBTs). The n-type doping is shown to be very effective for enhancing the tunneling-injection current from the emitter and thus for reducing the collector-current turn-on voltage. However, it is also revealed that an unnecessary increase in the doping level only degrades the current gain, especially in the low-current region. A higher doping level also increases the emitter junction capacitance. The optimized HBT structures with a 0.5-µm-wide emitter exhibit turn-on voltage as low as 0.78 V and current gain of around 80 at JC = 1 mA/µm2. They also provide a current-gain cutoff frequency, ft, of 280 GHz and a maximum oscillation frequency, fmax, of 385 GHz at VCE = 1 V and JC = 3 mA/µm2. These results indicate that the proposed HBTs are very useful for high-speed and low-power IC applications.

This paper describes the circuit design and measured performance of a high-speed digital-to-analog converter (DAC) for the next generation of coherent optical communications systems. To achieve high-speed and low-power operation, we used an R-2R current-steering architecture and devised timing alignment and waveform improvement techniques. A 6-bit DAC test chip was fabricated with InP HBT technology, which yields a peak ft of 175 GHz and a peak fmax of 260 GHz. The measured differential and integral non-linearity (DNL and INL) are within +0.61/-0.07 LSB and +0.27/-0.52 LSB, respectively. The measured spurious-free dynamic range (SFDR) is 44.7 dB for a sinusoidal output of 72.5 MHz at a sampling rate of 13.5 GS/s, which was the limit of our measurement setup. The expected ramp-wave outputs at a sampling rate of 24 GS/s are also obtained. The total power consumption is as low as 0.88 W with a supply voltage of -4.0 V. This DAC can provide low-power operation and a higher sampling rate than any other previously reported DAC with a resolution of 5 bits or more.

We fabricated a 2:1 multiplexer IC (MUX) with a retiming function by using 1-µm self-aligned InP/InGaAs/InP double-heterojunction bipolar transistors (DHBTs) with emitter mesa passivation ledges. The MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and output amplitude of 520 mV when measured on the wafer. When assembled in a module using V-connectors, the MUX operated at 113 Gbit/s with a 514-mV output amplitude and a power dissipation of 1.4 W.

An inter-modulation distortion (IMD) compensation method for thermal memory effect using a multistage RC-ladder circuit has been proposed. The IMD caused by the thermal memory effect on an InGaP/GaAs HBT amplifier was compensated for by inserting a multistage RC-ladder circuit in the base bias circuit of the amplifier. Since heat flux owing to self-heating in the transistor can be approximated with a multistage thermal RC-ladder circuit, the canceling of IMD by an additional electrical memory effect generated from the RC-ladder circuit is predicted. The memory effects cause asymmetrical characteristics between upper and lower IMD. The IMD caused by the memory effects is expressed as a vector sum of each origin. By adjusting an electrical reactance characteristic for sub-harmonics affected by the thermal memory effect in the amplifier circuit, the asymmetric characteristic is symmetrized. The parameters of the RC-ladder circuit were estimated so that the adjusted electrical reactance characteristic is reproduced in simulation. A fabricated InGaP/GaAs HBT amplifier with the thermal memory effect compensation circuit exhibited a symmetrized and suppressed IMD characteristics.

We investigated collector current spreading in InGaAs single heterojunction bipolar transistors (SHBTs) having a collector thickness of 75 nm. SHBTs were fabricated with three different emitter widths -- 200, 400, and 600 nm -- and the highest cutoff frequency that was obtained was 468 GHz. The relationship between the current density at the highest cutoff frequency and the emitter width could not be used to estimate the current spreading because it was independent of the collector-base voltage. However, the relationship between the current density with the increase in the total collector-base capacitance and the emitter width indicates current spreading in the collector. The current spreading was estimated to be approximately 90 nm.

An L-band 4-bit RL/RC-switched active phase shifter using differential switches is developed. It employs RL/RC circuits in the design of series feedback loops of the quadrature differential amplifier and achieves 90, 45, and 22.5of phase shift by switching on and off the RL/RC circuits alternatively. On the other hand, a 180phase shift is achieved with the use of a phase difference between the differential outputs. By cascading all four bits, an insertion gain of 16 to 23 dB, a phase error of less than 8.5, and an RMS phase error of 4.6have been achieved at 1 GHz.