Yasunori MIYAHARA Minoru NAGATA
This paper describes an automatic transistor model parameter generation technique for a circuit simulator which can take device geometry into account. An 'area factor' is used to generate model parameters for different transistor shapes; however, the conventional method could not reflect the actual geometry differences other than for the emitter area. This resulted in inaccurate model parameters and such parameters were not acceptable to accurately simulate circuits for RF ICs. The proposed technique uses actually measured parameters and process data for a reference transistor and generates the individual model parameters for different shape transistors. In this technique, the parasitic resistor values are calculated and fitted in place of directly extracting them from the measured data. This ensures a better estimate. The reference transistor is made sufficiently large to neglect measurement errors in generating the parasitic capacitors. Thus, the model parameters for a very small transistor can be generated accurately. The model generating procedure has been implemented as a pre-processor to SPICE. This technique enables a fast turn around for RF IC circuit design which uses various shape transistors.
This paper theoretically evaluates the external electro-optic (EO) sampling of high-speed electrical signals using poled polymers as materials for a proximity electric-field sensor. Based on the derivation of the half-wave voltage and the analysis of a static electric field coupled to the polymeric media placed over IC interconnections, invasiveness, voltage sensitivity, and spatial resolution have been discussed. The polymeric sensors have shown to be used in contact with the IC interconnections with negligibly small invasiveness, thus making polymeric sensors provide higher sensitivity and spatial resolution than inorganic crystals such as GaAs and KD*P.
Power-law decay of current for the application of step-function voltage observed for amorphous materials can be expressed by an admittance sa(0a1) of a linear diode using complex angular frequency s. It is shown that power-law decay can be interpreted as a superposition of exponential decays having fractally distributed relaxation times and simulated using RC networks. By use of a similar manner, admittance s-b (0b1) showing the relation of duality can be simulated using RL networks. According to these methods, we can synthesize the admittance involving non-integer exponents systematically.
Yasuyoshi OKADA Masahiro HAYASHI
We propose a new type of Graph Rewriting Systems (GRS) that provide a theoretical foundation for using the reduction method which plays an important role on analyze network reliability. By introducing this GRS, several facts were obtained as follows: (1) We clarified the reduction methods of network reliability analysis in the theoretical framework of GRS. (2) In the framework of GRS, we clarified the significance of the completeness in the reduction methods. (3) A procedure of recognizing complete systems from only given rewriting rules was shown. Specially the procedure (3) is given by introducing a boundary graph (B-Graph). Finally an application of GRS to network reliability analysis is shown.
Caiming ZHANG Takeshi AGUI Hiroshi NAGAHASHI Tomoharu NAGAO
A new method for interpolating boundary function values and first derivatives of a triangle is presented. This method has a relatively simple construction and involves no compatibility constraints. The polynomial precision set of the interpolation function constructed includes all the cubic polynomial and less. The testing results show that the surface produced by the proposed method is better than the ones by weighted combination schemes in both of the fairness and preciseness.
Mikio KOYAMA Hiroshi TANIMOTO Satoshi MIZOGUCHI
This paper describes design considerations for high frequency active BPFs up to 100 MHz. The major design issues for high frequency active filters are the excess phase shift in the integrators and high power consumption of the integrators. Typical bipolar transistor based transconductors such as the Gilbert gain cell and the linearized transconductor with two asymmetric emitter-coupled pairs have been analyzed and compared. It has been clarified that the power consumption of the linearized transconductor can be much smaller than that of the Gilbert gain cell because of its high transconductance to working current ratio while maintaining a signal to noise ratio of the same order. A simple high-speed fully differential linearized transconductor cell is proposed with emitter follower buffers and resistive loads for excess phase compensation. A novel gyrator based transformation for the LC ladder BPF has been introduced. This transformation has resulted in a structure with simple capacitor-coupled active resonators which exactly preserves the original transfer function. A fourth order 10.7 MHz BPF IC was designed using the proposed transconductors. It was fabricated and has demonstrated the usefulness of the proposed approach. In addition, an experimental 100 MHz second order BPF IC with Q=14 has been successfully implemented indicating the potential of the proposed approach.
Progress of speech recognition based on the hidden Markov model has made it possible to realize man-machine dialogue systems capable of operating in real time. In spite of considerable effort, however, few systems have been successfully developed because of the lack of appropriate dialogue models. This paper reports on some of technology necessary to develop a dialogue system with which one can converse comfortably. The emphasis is placed on the following three points: how a human converses with a machine; how errors of speech recognition can be recovered through conversation; and what it means for a machine to be cooperative. We examine the first problem by investigating dialogues between human speakers, and dialogues between a human speaker and a simulated machine. As a consideration in the design of dialogue control, we discuss the relation between efficiency and cooperativeness of dialogue, the method for confirming what the machine has recognized, and dynamic adaptation of the machine. Thirdly, we review the research on the friendliness of a natural language interface, mainly concerning the exchange of initiative, corrective and suggestive answers, and indirect questions. Lastly, we describe briefly the current state of the art in speech recognition and synthesis, and suggest what should be done for acceptance of spontaneous speech and production of a voice suitable to the output of a dialogue system.
In this paper, we investigate the discrepancy between a serial version and a parallel version of zero-knowledge protocols, and clarify the information "leaked" in the parallel version, which is not zero-knowledge unlike the case of the serial version. We consider two sides: one negative and the other positive in the parallel version of zero-knowledge protocols, especially of the Fiat-Shamir scheme.
Mingyong ZHOU Zhongkan LIU Jiro OKAMOTO Kazumi YAMASHITA
A high resolution iterative algorithm for estimating the direction-of-arrival of multiple wide band sources is proposed in this paper. For equally spaced array structure, two Unitary Transform based approaches are proposed in frequency domain for signal subspace processing in both coherent multipath and incoherent environment. Given a priori knowledge of the initial estimates of DOA, with proper spatial prefiltering to separate multiple groups of closely spaced sources, our proposed algorithm is shown to have high resolution capability even in coherent multipath environment without reducing the angular resolution, compared with the use of subarray. Compared with the conventional algorithm, the performance by the proposed algorithm is shown by the simulations to be improved under low Signal to Noise Ratio (SNR) while the performance is not degraded under high SNR. Moreover the computation burden involved in the eigencomputation is largely reduced by introducing the Pesudo-Hermitian matrix approximation.
Junji NANJO Kamal Abu Hena MOSTAFA Kiyoyasu TAKADA Yutaka KOBAYASHI Toshihide MIYAZAKI Shigeru NOMURA
Formation of thin insulating SiO2 films by anodic oxidation of silicon was studied as a part of investigating an alternative method of fabricating low-cost silicon MIS solar cells. Anodization in the constant-voltage mode was carried out in nonaqueous ethylene glycol solution. The film thickness was carefully measured using an ellipsometer of wavelength 6238 . MIS cell performance was evaluated by comparing the open circuit voltage VOC and the short circuit current density ISC with those of the bare Schottky cell (without anodization) under illumination by a tungsten lamp. It was found that anodization in the constant-voltage mode can increase VOC without reducing ISC, and that anodization in the constant-voltage mode is more controllable and reproducible. The optimun formation voltage which gives the maximum VOC of the MIS cell depends on the forming voltage of oxide. A brief discussion on the mechanism for VOC increase is given.
This paper was written for LSI engineers in order to demonstrate the effect of optical interconnections in LSIs to improve both the speed and power performances of 0.5 and 0.2 µm CMOS microprocessors. The feasibilities and problems regarding new micronsize optoelectronic devices as well as associated electronics are discussed. Actual circuit structures clocks and bus lines used for optical interconnection are discussed. Newly designed optical interconnections and the speed power performances are compared with those of the original electrical interconnection systems.
Kazuhiro TSURUTA Mitsutaka KATADA Seiji FUJINO Tadashi HATTORI
A bipolar power transistor which has beveled side walls with an exposed PN junction has been fabricate using silicon wafer direct bonding technique. It is suitable for a power IC which has a control circuit formed on a SOI structure and a vertical power transistor. It can achieve the breakdown voltage of more than 1000 V in smaller chip size than conventional power devices and reduce the ON-resistance because it is possible to optimize the thickness and resistivity of its low impurity collector layer. Angles of beveled side walls were determined by simulating the electric fields in the devices. As a result, it was found that both NPN and PNP bipolar power transistors with breakdown voltages of 1500 V could be fabricated.
Yoshihiro KANEKO Shoji SHINODA Kazuo HORIUCHI
A vertex-capacitated network is a graph whose edges and vertices have infinite positive capacities and finite positive capacities, respectively. Such a network is a model of a communication system in which capacities of links are much larger than those of stations. This paper considers a problem of realizing a flow-saturation in an undirected vertex-capacitated network by adding the least number of edges. By defining a set of influenced vertex pairs by adding edges, we show the follwing results.(1) It suffices to add the least number of edges to unsaturated vertex pairs for realizing flow-saturation.(2) An associated graph of a flow-unsaturated network defined in this paper gives us a sufficient condition that flow-saturation is realized by adding a single edge.
Ikuo SUZUKI Minoru MURAKAMI Masaki MAEDA
Chaotic behavior in a series resonance circuit with a ferroelectric triglycine sulfate (TGS) crystal was observed just below the ferroelectric phase transition temperature. We have analyzed the nonlinear responses by applying external electric fields to the crystal. The computer simulation was made for the modified forroelectric hysteresis loops to realize the experimental results. The fractal correlation dimension was determined to be ν=1.8 in the chaotic phase.
Chunxiang CHEN Masaharu KOMATSU Kozo KINOSHITA
In high-speed packet networks, protocol processing overhead time becomes remarkable in determining the system performance. In this paper, we present a new Selective-Repeat ARQ scheme (called Block SR-ARQ sheme), in which a packet is transmitted or retransmitted in the same way as basic SR-ARQ scheme, but a single acknowledgement packet is used to acknowledge a block of packets. The maximum number of packets acknowledged by an acknowledgement packet is defined as block size. We analyze the system throughput and the average packet delay over the system, and the accuracy of approximately analyzed results is validated by simulation. Furthermore, we show that there exists an optimal block size which obtains both the maximum throughput and the minimum average packet delay.
We analyzed vergence change by moving both the target and the subject toward depth direction simultaneously. It has been suggested that the command for vergence movement caused by depth-direction-head-movement and that caused by target movement are generated separately, then combined in the oculomotor system.
Yukio ISHIBASHI Fujihiko MATSUMOTO
Up to present, some automatically tunable active RC filters have been proposed for the monolithic integrated continuous-time filters. In this paper a synthesis method of monolithic active RC filters is presented, whose characteristic is hardly dependent on temperature, supply voltage and so on, theoretically. First, this paper describes a variable integrator controlled by bias current. Second, a resistor controlled current source circuit (RCCS) is also proposed, which contains the voltage controlled current source (VCCS) being identical with that used in the realization of the integrator and whose current is controlled by an external resistor. The use of this VCCS in the RCCS can completely compensate the variation of the integrator characteristics. Finally, these circuits are applied to realize a third-order elliptic low-pass filter, which is simulated on PSPICE. From the simulations, we obtain excellent results as follows: The deviation of gains in the passband due to the variation of temperature with a range of -10 to 60 is within 0.02 dB; A total harmonic distortion with a 1 Vp-p input voltage at 100 kHz is less than 0.4% when the cut-off frequency is 1 MHz and the supply voltage is 5 V.
Toshiro SATO Michio HASEGAWA Tetsuhiko MIZOGUCHI Masashi SAHASHI
A newly developed planar inductor and its application to dc-dc converters are described. The planar inductor consists of a planar spiral coil and soft magnetic sheets, it has a small size (11110.8mm), 33µH inductance and a maximum quality factor of 14. The step down chopper dc-dc converter has been developed by using planar inductor, which has small size (20154mm), 5V-2W typical output and output power/volume ratio of 1.7W/cc. The switching converter can be miniaturized by using the planar inductor.
Tadahito AOKI Yousuke NOZAKI Yutaka KUWATA Tohru KOYASHIKI
This paper describes configuration and operation of a high-frequency link resonant inverter using cycloconverter techniques. In this inverter, a resonant link high-frequency voltage generated in a primary resonant inverter is isolated by a high-frequency transformer, then directly converted into a resonant link low-frequency voltage in a cycloconverter. The switching losses and surge voltage levels can be reduced by making all switches in the primary inverter and the cycloconverter operate at zero voltage. The relationship between characteristic impedance of the resonant circuit and the conversion efficiency, and the distortion factor characteristics of the output voltage waveforms are discussed by comparing of analytical and experimental results.
Yu Rong HOU Atsushi OHNISHI Yuji SUGIYAMA Takuji OKAMOTO
There have been few studies on formal approaches to the specification and realization of asynchronous sequential circuits. For synchronous sequential circuits, an algebraic method is proposed as one of such approaches, but it cannot be applied to asynchronous ones directly. This paper describes an algebraic method of specifying the abstract behavior of asynchronous sequential circuits. We select an daisy chain arbiter as an example of them. In the arbiter, state transitions are caused by input changes, and all the modules do not always make state transitions simultaneously. These are main obstacles to specify it in the same way as sychronous sequential circuits. In order to remove them, we modify the meaning of input in specifications and introduce pseudo state transitions so that we can regard all the modules as if they make state transitions simultaneously. This method can be applied to most of the other asynchronous sequential circuits.