This letter presents a new algorithm for echo cancellers, which prevents the reduction of echo return loss due to a double-talk. The essence of the algorithm is to introduce signal delays to avoid the reduction. A convergence condition in the algorithm was examined by using the IIR filter expression of the NLMS algorithm, and it was concluded that the IIR filter should be a low pass filter with unity gain. The condition is accomplished by selecting a small step gain.

The test pattern generation for sequential circuits is more difficult than that for combinational circuits due to the presence of memory elements. Therefore we proposed a method for synthesizing sequential circuits with testability in the level of state transition table. The state transition table is augmented by adding extra two inputs so that it possesses a distinguishing sequence, a synchronizing sequence, and transfer sequences of short length. In this case the checking sequence which do a complete verification of the circuit can be test pattern. The checking sequence have been impractical due to the longer checking sequence required. However, in this paper, we have discussed the condition to reduce the length of checking sequence, then by using suitable state assignment codes sequential circuits with much shorter checking sequences can be realized. A heuristic algorithm of the state assignment which reduce the length of checking sequence is proposed and the algorithm and reduced checking sequence are presented with simple example. The state assignment is very simple with the state matrix which represents the state transition. Furthermore some experimental results of automated synthesis for the MCNC Logic Synthesis Workshop finite state machine benchmark set have shown that the state assignment procedure is efficient for reducing checking sequences.

In this paper, we present an efficient method for the fault simulation of the reconvergent fan-out stem. Our method minimizes the fault propagating region by analyzing the topology of the circuit, whose region is smaller than that of Tulip's. The efficiency of our method is illustrated by experimental results for a set of benchmark circuits.

More than 500 articles in the field of analog circuits in the last two decades are surveyed and about 170 of which are listed in the References. These are mainly included in the Transactions of IEICE. The survey are made on the five fields; general analog circuit technology, modeling and simulation, active RC filters, switched capacitor circuits, and A/D and D/A converters.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.

Intermittent chaos was observed in the silicon thyristor circuit without external elements of L and C, under the condition of ac excitation at the anode. Lorenz plot reconstructed from the experimental waveform and the numerical simulation of this kind of intermittency fairly agreed with each other.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

A strictly nonblocking 88 matrix switch was designed and fabricated using silica-based planar lightwave circuits (PLC) on a silicon substrate. The average insertion loss was 11 dB in the TE mode and 11.3 dB in the TM mode. The average switch element extinction ratio was 16.7 dB in the TE mode and 17.7 dB in the TM mode. The accumulated crosstalk was estimated to be 7.4 dB in the TE mode and 7.6 dB in the TM mode. The driving power of the phase shifter required for switching was about 0.5 W and the polarization dependence of the switching power was 4%. The switching response time was 1.3 msec. The wavelength range with a switch extinction ratio of over 15 dB was 1.31 µm30 nm.

Numerical solutions for the near-field of microstrip antennas are presented. The field distribution is calculated by taking the inverse Fourier transform involving the current distribution with the help of the spectral-domain moment method. A new technique to save the computation time is devised, and the field pattern of the circularly polarized antenna is illustrated.

This system called COKIS automatically extracts knowledge about C functions from the UNIX on-line manual by using its description paragraph and the user can interactively inquire to the system in order to know about UNIX C functions. The idea is motivated on the one side to free users from being involved in an exhaustive knowledge acquisition in the past, and to examine problems in understanding knowledge itself on the other. We propose Memory Processor which is implemented to realize extracting knowledges from corpus and processing dialogues in the inquiry system at the same modules.

The performance of analog circuits is strongly influenced by their layout. Performance specifications are usually translated into physical constraints such as symmetry, common orientation, and distance constraints among certain components. Automatic digital layout tools can be adopted and modified to deal with the imposed performance constraints on the analog layout. The selection and modifications of algorithms to handle the analog constraints became the area of research in analog layout systems. The existing systems are characterized by the use of stochastic optimization techniques based placement, grid based or channel routers, and lack of compaction. In this paper, algorithms for analog circuit placement, routing, and compaction are presented. The proposed algorithms consider the analog oriented constraints, which are important from an analog layout point of view, and reduce the computation cost. The placement algorithm is based on a force directed method and consists of two main phases, each of which includes a tuning procedure. In the first phase, we solve a set of simultaneous linear equations, based upon the attractive forces. These attractive forces represent the interconnection topology of given blocks and some specified constraints. Symmetry constraint is considered throughout the tuning procedure. In the second phase, block overlap resulting from the first phase is resolved iteratively, where each iteration is followed by the symmetry tuning procedure. Routing is performed using a line expansion based gridless router. Routing constraints are taken into account and several routing priorities are imposed on the nets. The compactor part employs a constraint graph based algorithm while considering the analog symmetry constraints. The algorithms are implemented and integrated within an analog layout design system. An experimental result for an OP AMP provided by MCNC benchmark is shown to demonstrate the performance of the algorithms.

AlGaAs/GaAs HBT ICs for high bit-rate optical transmission systems, such as preamplifier, D-F/F, differential amplifier, and laser driver, have been newly developed using the hetero guard-ring fully self-aligned HBT (HGFST) fabrication process. In this process, the emitter mesa is ECR-RIBE dry etched using a thick emitter-metal system of WSi and Ti-Pt-Au as etching mask, and a hetero guard-ring composed of a depleted AlGaAs layer is fabricated on p GaAs extrinsic base regions. This process results in highly uniform HBT characteristics. The preamplifier IC exhibits a DC to 18.5-GHz transimpedance bandwidth with a transimpedance gain of 49 dBΩ. The rise time and fall time for the D-F/F IC are 30 and 23 ps, respectively. The laser driver IC has a 40-mAp-p output current swing. The differential amplifier exhibits a DC to 12.1-GHz bandwidth with a 14.2-dB power gain.

A least squares approximation method of recursive digital filters for finite interval response with zero value outside the interval is presented. According to the characteristic of the method, the modified Gauss Method is utilized in iteratively determining design parameters. Convergence, together with the stability of the resulting filter, are guaranteed.

Oversampled analog-to-digital (A/D) converters based on sigma-delta (ΣΔ) modulation are attractive for VLSI implementation because they are especially tolertant of circuit nonidealities and component mismatch. Oversampled ΣΔ modulator has some points which must be improved. Some of these problems are based on the small input signal and the integrator leak. In this paper,ΣΔ A/D converter having a dither circuit to improve the linearity and the compensation technique of the integer leak are presented. By the simulation, the most suitable dither to improve the linearity of the modulator is obtained as follows: the amplitude is 1/150 of input signal maximum amplitude, the frequency is 4-times of the signal-band. Using the compensation circuit of the integrator leak, 72 dB of dynamic range is obtained when op-amp gain is 30 dB.

Switched-current (SI) is a current-mode analog sampled-data signal processing technique realizable in standard digital CMOS technologies. In this paper, new switched-current (SI) mirrors using OTAs (operational transconductance amplifiers) are proposed. These circuits are less sensitive to clock-feedthrough noise than conventional SI mirrors by virtue of linear I-V/V-I transformations. In addition, the current gain of the proposed mirror is electronically tunable. Not only inverting mirrors but also noninverting mirrors can be realized by this method.

This paper deals with the uniqueness of a solution of the basic equation obtained from the analysis of resistive circuits including ideal diodes. The equation in consideration is of the type of (A-)X=b, where A is a constant matrix, b a constant vector, X an unknown vector satisfying X 0, and a diagonal matrix whose diagonal elements take the value 0 or 1 arbitrarily. The necessary and sufficient conditions for the equation to have a unique solution X 0 for an arbitrary vector b are shown. Some numerical examples are given for the illustration of the result.

Focused Ion Beam (FIB) trimming techniques for circuit optimization for GaAs MMICs by adjusting the parameters of IC components such as resistors, capacitors, microstrip lines, and FETs have been developed. The adjustment is performed by etching of the components and depositing of metal films for micro-strip lines. This technology turned out to be in need of only half a day to optimize the circuit pattern without any further wafer processes, while a conventional method that is comprised of revising mask pattern and following several cycles of wafer process has needed 0.5-1.0 year requiring huge amount of development cost. This technology has been successfully applied to optimization of an X-band low dissipation current single stage MMIC amplifier, and has shown its great feasibility for shortening the turn around time.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

This paper presents a general form and a set of basic gates to implement (K+1)-valued PLA structure logic circuits. A complete fault analysis on the proposed circuit has been done and it is shown that all fanout stem faults can be collapsed to branch faults. A procedure for fault collapsing is derived. For any function implemented in the (K+1)-valued circuit, the number of remaining faults is smaller than that of the 2-valued circuit after the collapsing, where the value of K is dependent on the number of outputs and the assignment of the OR plane of the 2-valued logic circuit.