Recent achievements in low-voltage and low-power circuit techniques are reported in this paper. DC current in low-voltage CMOS circuits stemming from the subthreshold current in MOS transistors, is effectively reduced by applying switched-power-line schemes. The AC current charging the capacitance in DRAM memory arrays is reduced by a partial activation of array blocks during the active mode and by a charge recycle during the refresh mode. A very-low-power reference-voltage generator is also reported to control the internal chip voltage precisely. These techniques will open the way to using giga-scale LSIs in battery-operated portable equipment.

A superconducting multichip module using Nb/Polyimide on a mullite multilayer ceramic substrate has been developed for Josephson LSI circuits. The Nb/Polyimide stacked layers on the mullite multilayer ceramic substrate makes it possible to fabricate superconducting off-chip wiring for control signal line. We named the MCM "SuperMCM". The superconducting transmission line is designed to have the characteristic impedance of 14 Ω to match with the Josephson devices. The superconducting critical temperature, critical current density and critical current at a via hole are 8.5 K, 8.2105 A/cm2 and 2.5 A, respectively. The SuperMCM also provides matching circuits employing quarter wavelength striplines for driving Josephson LSI circuits at a microwave frequency, and DC bias circuits in the mullite multilayer ceramic substrate. The characteristics of the matching circuit is measured in the frequency range up to 3.6 GHz and the microwave current gain of 20 dB is obtained at 1.2 GHz, which revealed that the SuperMCM has the ability to drive the Josephson LSI circuits at more than 1.2 GHz clock speed.

This paper describes CMOS embedded RAMs we developed utilizing 1.3 µm and 0.8 µm process technologies. Our goal was to achieve high-performance switching for digital communication systems. Because such switching can best be obtained by using high-performance embedded RAMs, we used 0.8 µm process technology and developed a 4 kW9 b single-port embedded RAM with 5 ns access time and 100 mW power dissipation during32 MHz operation, and a 1 kW9 b dual-port embedded RAM with 3.7 ns access time and 100 mW power dissipation during 40 MHz operation. We implemented these RAMs on one chip in developing three time-switch VLSIs, one buffer memory VLSI for ATM switches, and two cross-connect switch VLSIs.

The byte error locating codes specify the byte location in which errors are occurred without indicating the precise location of erroneous bit positions. This type of codes is considered to be useful for fault isolation and reconfiguration in the fault-tolerant computer systems. In this paper, difference between the code function of error-location and that of error-correction/error-detection is clarified. With using the concepts of unidirectional byte distance, unordered byte number and ordered byte number, the necessary and sufficient conditions of the unidirectional byte error locating codes are demonstrated.

An analog circuit is devised which selects and outputs the kth largest element among n input voltages. The circuit is composed of n basic transconductance amplifiers connected mutually with an O(n) length wire, thus the complexity of the circuit is O(n). The circuit becomes particularly simple for the case of the selection of the median of inputs.

This paper presents a low-power 8-valued cellular array VLSI for high-speed image processing based on logical neighborhood operations with 33 windows. This array is useful for performing low-level image processing such as noise removal and edge detection, in intelligent integrated systems where immediate response to input change as well as high throughput is needed. In order to achieve high-speed image processing, template matching for neighborhood operations can be performed in parallel on each row. Each row of the image is operated in a pipelining manner. The direct 8-valued encoding of the matched results for three different 33 masks makes it possible to reduce the number of operations by one-third. In the hardware implementation, the matching cell for logical neighborhood operations can be implemented compactly using MOS transistors with different threshold voltage, which are programmed by multiple ion implants. Moreover, a new literal circuit for detecting multiple-valued signals using a dynamic design style eliminates hazards due to timing skews in the difference of various input voltage levels, so that the dynamic power dissipation of the proposed circuit is greatly reduced. Finally, it is demonstrated that the processing time of the proposed cellular array is reduced to about 40 percent in comparison with that of a corresponding binary circuit when power dissipation/area = 0.3 W/100 mm2.

This paper proposes a group demodulator that employs multi-symbol chirp Fourier transform to demodulate pulse shaped and time asynchronous signals without degradation; this is not possible with conventional group demodulators based on chirp Fourier transform. Computer simulation results show that the bit error rate degradation of the proposed group demodulator at BER=10-3 is less than 0.3dB even when a root Nyquist (α=0.5) filter is used as the transmission pulse shaping filter and the symbol timing offset between the desired channel and the chirp sweep is half the symbol period.

An asynchronous spread spectrum (SS) modem for 2.4-GHz wireless LAN has been implemented using an efficient ZnO-SiO2-Si surface acoustic wave (SAW) convolver. The design of the highly efficient SAW convolver was developed at Tohoku University and commercially manufactured by Clarion Co., Japan. The modem can operate under full-duplex transmission in the same frequency range of the 2.4-GHz SS band. The SS modem is based on a direct-sequence/code-shift-keying (DS/CSK) method for the modulation. Pseudo-noise (PN) codes are chosen from a preferred pair of 127-chip m-sequences and the code rate is 14MHz. The asynchronous demodulation is simply realized utilizing the coherent correlation characteristics of the SAW convolver. Under full-duplex transmission, the self-jamming caused by a transmitted signal in the modem itself is effectively reduced by an RF isolator and the SS processing gain. The implemented modem has been tested using a coaxial cable with attenuator. A bit error rate of 10-6 under full-duplex transmission is observed at 78.3dB of a desired to undesired signal ratio. The effective range is estimated on the basis of two-path propagation model. From self-jamming rejection of 78.3dB, the effective range under real-time full-duplex is estimated to be about 200m.

In this paper we propose a method for increasing the reliability in multiprocessor realization of lowpass and highpass FIR digital filters possessing a maximally flat magnitude response. This method is based on the use of array realization of the filter which has been proposed earlier by the authors. It is shown that if a processing module of the array functions erroneously, it is possible to exclude the module and still obtain a lowpass FIR filter. However, as a price we should tolerate a slight degradation in the magnitude response of the filter that is equivalent to a wider transition band. We also analyze the behavior of the filter when our proposed schemes are implemented on more than one module. The justification of our approach is based on that a slight degradation of the spectral characteristics of a filter may be well tolerated in most filtering applications and thus a graceful degradation in the frequency domain can sufficiently reduce the vulnerability to errors.

This paper presents a discrete Fourier analyzer using analog VLSI technology. An analog current-mode technique is employed for implementing it by a regular array structure based on the straight-forward discrete Fourier transform (DFT) algorithm. The basic components are 1-dimensional (1-D) analog current-mode multiplier array for fixed coefficient multiplication, two-dimensional (2-D) analog switch array and wired summations. The proposed scheme can process speedily N-point DFT in a time proportional to N. Possibility of the realization of the analog DFT VLSI based on 1 µm technology is discussed from the viewpoints of precision, speed, area, and power dissipation. In the case of 1024-point DFT, the standard deviation of the total error is estimated to be about 2%, the latency, or processing time is about 110 µs, and the signal sample rate based on a pipeline manner is about 4.7 MHz. A prototype MOS integrated circuit of the 16-point multiplier array has been implemented and a typical operation using the multiplier array has been confirmed.

It is demonstrated that the enhancement in the functional capability of an elemental transistor is quite essential in developing human-like intelligent electronic systems. For this purpose we have introduced the concept of four-terminal devices. Four-terminal devices have an additional dimension in the degree of freedom in controlling currents as compared to the three-terminal devices like bipolar and MOS transistors. The importance of the four-terminal device concept is demonstrated taking the neuron MOS transistor (abbreviated as neuMOS or νMOS) and its circuit applications as examples. We have found that any Boolean functin can be realized by a two-stage configuratin of νMOS inverters. In addition, the variable threshold nature of the device allows us to build real-time reconfigurable logic circuits (no floating gate charging effect is involved in varying the threshold). Based on the principle, we have developed Soft-Hardware Logic Circuits and Real-Time Rule-Variable Data Matching Circuits. A winner-take-all circuit which finds the largest signal by hardware parallel processing has been also developed. The circuit is applied to building an associative memory which is different from Hopfield network in both principle and operation. The hardware algorithm in which binary, multivalue, and analog operations are merged at a very device level is quite essential to establish intelligent information processing systems based on highly flexible, real-time programmable hardwares realized by four-terminal devices.

This paper proposes a request-grant-type multiple access control called bandwidth-request labeled-slot multiple access (BLMA) for wireless LANs. BLMA employs slotted ALOHA in the request stage and has an algorithm to avoid unfair access due to the capture effect in this stage. In BLMA, terminals transmit data using fixed length slots called fragment slots in the transmission stage. The base station assigns the fragment slots one by one to terminals for peer-to-peer communication in which terminals communicate directly. It also controls the retransmission based on the stop and wait automatic repeat request scheme. The base station retransmits data for the source terminal as much as it can. BLMA provides simple and fair access control, efficient link utilization, and easy implementation. It also allows modes to be easily changed automatically from peer-to-peer communication to store-and-forward communication in which terminals communicate via the base station. Design concepts of a wireless MAC discussed and details of BLMA are described. The evaluation results of the BLMA are also shown.

We study robot navigation in unknown environment with rectangular obstacles aligned with the x and y axes. We propose a strategy called the modified-bian heuristic, and analyze its efficiency. Let n be the distance between the start point and the target of robot navigation, and let k be the maximum side length among the obstacles in a scene. We show that if k=(o(n) and if the summation of the widths of the obstacles on the line crossing the target and along the y axis is o(n), then ratio of the total distance walked by the robot to the shortest path length between the start point and the target is at most arbitrarily close to 1+k/2, as n grows. For the same restrictions as above on the sizes of the obstacles, the ratio is also at most arbitrarily close to 1+3/4n, as n grows, where is the summation of lengths of the obstacles in y axis direction.

It is of significantly importance in relation to the problem of diagnosis of deviation faults in linear analog circuits to check whether or not it is possible to uniquely determine the element-values in a given linear analog circuit from the node-voltage measurements at its accessible nodes and then of giving a method for actual computation of the element-values if it is possible, under the assumption that i) the circuit is of known topology (and of known element-kinds if possible) and ii) the actual value of each element-value of the circuit almost always deviates from the design value and is not known exactly. In this paper, the problem of checking the unique determinability of the element-values is called the element-value determinability problem, and its solutions which have been obtained until now are reviewed in perspectives to designing a publicly available user-oriented analog circuit diagnosis system.

This paper describes the relaxation-based algorithms with the dynamic partitioning technique for bipolar circuit analysis. In this technique, a circuit is partitioned dynamically based on the consideration of the operating region of specified bipolar devices. This technique has been used already in the waveform relaxation method. In this paper, the dynamic circuit partitioning technique is implemented in the Iterated Timing Analysis (ITA). First, the dynamic partitioning method and its validity are described. Next, the present ITA is applied to the transient simulation of several digital bipolar circuits and compared with the waveform relaxation method.

Binary decision diagrams (BDD's) are graph representations of Boolean functions, and at the same time they can be regarded as a computational model. In this paper, we discuss relations between BDD's and other computational models and clarify the computational power of BDD's. BDD's have the property that each variable is examined only once according to a total order of the variables. We characterize families of BDD's by on-line deterministic Turing machines and families of permutations. To clarify the computational power of BDD's, we discuss the difference of the computational power with respect to the way of reading inputs. We also show that the language TADGAP (Topologically Arranged Deterministic Graph Accessibility Problem) is simultaneously complete for both of the class U-PolyBDD of languages accepted by uniform families of polynomial-size BDD's and the clas DL of languages accepted by log-space bounded deterministic Turing machines. From the results, we can see that the problem whether U-PolyBDD U-NC1 is equivalent to a famous open problem whether DL U-NC1, where U-NC1 is the class of languages accepted by uniform families of log-depth constant fan-in logic circuits.

For the study of the biological effects of ELF (Extremely Low Frequency) electric fields, the perception mechanism of ELF electric fields was analyzed. When a human body is exposed to an electric field, the hair on the body surface moves due to the electric force exerted on the hair. In theoretical analysis, it was shown that the force is approximately proportional to the dielectric constant of hair and the spatial gradient of the square of the electric field at the hair. The dielectric constant of hair was measured with different temperatures and humidities of the surrounding air. A technique was developed to estimate the electric force exerted on a hair during the field exposure. After experiments with model hair, the technique was applied to a body hair of a living human being. It was found that the force increased with field strength and relative humidity. The variations of the force agreed well with those expected from the theoretical analysis and the measurement of hair dielectric constants. These results explain the cause of the reported variation in the threshold of biological effects of an electric field. The results will help to establish a practical safety standard for the held exposure.

A new design methodology is proposed and analyzed for the design of ternary logic systems. In the new ternary logic systems, no conversions among radices are required and only the two-state ternary literals associated with the ternary signals are transmitted in the whole system. With the new design methodology, the ternary systems can be realized by the dynamic CMOS logic circuits which are simple and fully compatible with those of the conventional binary logic circuits in process, power supply, and logic levels. A new dynamic differential logic called the CMOS Redundant Differential Logic (CRDL) is also developed to increase the logic flexibility and the circuit performance. Using the new design methodology and the CRDL circuits, the multiplier with redundant binary addition tree is designed in both non-pipelined and pipelined systems. The experimental chip has been fabricated and measured, which successfully verifies the correctness of the logic functions and the speed performance of the designed circuits.

A simple method for separating the dissipation factors associated with both conductor losses and dielectric losses of printed circuit boards in microwave frequencies is presented. This method utilizes the difference in dependence of two dissipation factors on the dimensions of bounded stripline resonators using a single printed circuit board specimen as a center strip conductor. In this method, the separation is made through a procedure involving the comparison of the measured values of the total dissipation factor with those numerically calculated for the resonators. A method, which is based on a TEM wave approximation and uses Green's function and a variational principle, is used for the numerical calculation. Both effective conductivity for three kinds of industrial copper conductor supported with a substrate of polymide film and dielectric loss tangent of the substrates are determined using this method from the values of the unloaded Q measured at the 10 GHz region. Radiation losses from the resonator affecting the accuracy of the separation are discussed, as well as the values of the effective conductivity of metals on the polyimide substrate which is calculated using the above method. The resulting values of the effective conductivity agree with those using the triplateline method within 10%.

We propose a beam tracing frame which shifts together with either the guiding structure or the beam propagation in optical circuits. This frame is adaptive to the beam propagation analysis based on the finite-element method and can reduce the computational window size.