The aim of this study is to evaluate mental workload (MWL) quantitatively by HRV (Heart Rate Variability) measures. The electrocardiography and the respiration curve were recorded in five different epochs (1) during a rest condition and (2) during mental arithmetic tasks (addition). In the experiment, subjects added two numbers. The work levels (figures of the number in the addition) were set to one figure, two figures, three figures and four figures. The work level had effects on the mean percent correct, the number of answers and the mean processing time. The psychological evaluation on mental workload obtained by the method of paired comparison increased with the work level. Among the statistical HRV measures, the number of peak and trough waves could distinguish between the rest and the mental loading. However, mental workload for each work level was not evaluated quantitatively by the measure. The HRV measures were also calculated from the power spectrum estimated by the autoregressive (AR) model identification. The ratio of the low frequency power to the high frequency power increased linearly with the work level. In conclusion, the HRV measures obtained by the AR power spectrum analysis were found to be sensitive to changes of mental workload.

This paper presents a design of low-power CMOS OTA-C filters suitable for on-chip integration of advanced monolithic system LSIs that have analog I/O and digital signal processing capability. First, we discuss the distortion of MOS cross-coupled circuits which have a quite low distortion when the MOS FETs have the square law characteristics. Considering the nonidealities of MOS FET, however, we find that the third harmonic component of signal dominates the total harmonic distortion (THD) of the cross-coupled pair circuit. We propose a new architecture to reduce the 3rd harmonic component. Low distortion operational transconductance amplifiers (OTA) which consist of the proposed low distortion cross-coupled pair are applied to the realization of OTA-Capacitor filters. The SPICE simulation shows that the THD of the filter is 0.0047% and the power dissipation is 22.6 mW.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

The consequences of energy transport related effects like velocity overshoot on the performance of bipolar transistors have already been studied previously. So far however most of the applied models were only 1D and it remained unclear whether such effects would have a significant influence on important quantities like ECL gate delay accessible only on the circuit level. To the authors' best knowledge in this paper for the first time the consequences of energy transport related effects on the circuit level are investigated in a rigorous manner by mixed level device/circuit simulation incorporating full 2D numerical hydrodynamic models on the device level.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

OTA (Operational Transconductance Amplifier) is a useful circuit in analog signal processing systems, especially in high-frequency applications. Important features of OTA are: infinite input impedance, electrically changeable transconductance (Gm), and much wider operation range without negative feedback such as in OPamp applications. The good linearity of OTA over wide input range is necessary to extend the application fields of OTA. Several techniques are developed to extend the input range with good linearity. In this paper, a highly-linear CMOS-OTA operating under 1 V power supply, is proposed. The concept of the proposed OTA is based on class-AB operation of two n-channel MOSFETs in the saturation region. By improving the input stage circuits, wide input range can be achieved. SPICE simulations are performed to verify the performance of the proposed OTA.

An HDTV still-picture camera that uses four PAL CCD sensors has been developed for use as a high-speed, high-resolution image reader. The CCD sensors are optically coupled to a single lens by a pyramidal mirror. Each CCD sensor reads a quarter of the image and the four quarter-images are combined into one HDTV picture. Discontinuities at the lines where the four images join can be eliminated by white- and dark-level correction and gamma correction. Moreover, smoothing processing using a weighted-mean method is performed to produce a seamless picture. With this processing the camera can consistently produce seamless pictures.

The Synchronous Optical Network (SONET) technology offers technical possibilities to build high speed transport networks and enables the operator to react quickly to the customers' capacity requirements. Furthermore the advanced SONET equipment, with standardized control and operation features, provides opportunities for new services, such as broadband services, and cost-effective ways to enhance existing services, such as network survivability improvement. But SONET technology can also create a certain degree of complexity in building cost-efficient network, especially in case of SONET Self-Healing Ring (SHR). It is a challenge for network planner to find an effective way to select the most economical SONET ring, or combination of rings, for given demands between a set of nodes that are supposed to be connected in a certain type of ring configuration. Three types of ring are standard today: path unidirectional, 2-fiber line protection bidirectional and 4-fiber line protection bidirectional. For a given network, the choosing of ring architecture based on economical considerations involves two major factors. They are capacity requirement and equipment cost. Capacity requirements of different SONET ring architectures depend upon different conditions. While facility line rate, which is a key factor in deciding what kind self-healing ring can be deployed economically on these requirements. Routing decisions play a key role in deciding the ring capacities required, especially for bidirectional rings. In the paper, we will make the economic study on how SONET SHR architecture works out with a variety of demand patterns, to find criteria for ring selection. We first present two efficient demand loading algorithms for BSHR capacity calculation, and then analyze the results from their application on a variety of demand patterns. The economic study for SONET SHR networks based on different architectures are also discussed.

This paper proposes a novel method to realize highly linear MOS circuits using MOSFETs in the nonsaturation region. The proposed method is based on the cancellation of nonlinearity of two MOSFETs by using a current inversiontype negative impedance converter. First, grounded and floating resistor realizations are discussed. Next, by exploiting the MOS resistor circuits, gyrators and inductors are realized. As an application example, a third-order doubly-terminated LC filter is simulated. SPICE analysis shows low total harmonic distortions, excellent controllability and small gain error in the passband.

The increasing size and complexity of integrated circuits has lead to the development of advanced algorithms and techniques for circuit simulation. The majority of circuit simulators rely on the Newton-Raphson algorithm for the solution of nonlinear equations that arise from the circuit description. Unfortunately, a good estimate of the root to be found is needed for the algorithm to converge. The convergence rate of the algorithm is quadratic once the method gets "close enough" to the solution, but before reaching this point the method may follow a complex route through unrealistic values of the circuit variables, leading eventually to divergence. Simulations performed with SPICE on several test circuits reveal that during the first iterations of the Newton-Raphson algorithm internal node voltages exceed the power supply voltage of several orders of magnitudes even for simple circuits. A new simulation program called MUSIC (Multilevel Simulator for Integrated Circuits) has been developed to overcome these drawbacks. In MUSIC the circuit to be simulated is decomposed in subcircuits, which may contain instances of other subcircuits up to any nesting level. Subcircuits are then simulated independently with a multilevel Newton algorithm permitting to reduce both the large oscillations that circuit variables undergo during the simulation process and the number of iterations necessary for the circuit to converge. The novel feature of this multilevel algorithm is the propagation of the already calculated terminal voltages, which become known after a subcircuit has converged, to the subcircuits connected to same terminals. In this way the information regarding node voltages is propagated through the network without constraining conditions that do not have physical counterpart. Simulations performed on chains of inverters and a 4-bit full adder evidence how MUSIC is able to improve the convergence rate and to reduce the intermediate voltage spikes.

The power transfer characteristics of a symmetric nonlinear directional coupler (NLDC) are analyzed rigorously using the beam propagation method based on the finite difference scheme. The NLDC consists of two linear waveguides separated by a Kerr-like nonlinear gap layer. The change of nonlinear refractive index along the coupler is precisely evaluated by making use of the second-order iteration procedure with respect to a small propagation length. For the incidence of TE0 mode of the isolated linear waveguide, the highly accurate numerical results are obtained for the behavior of power transfer, and the coupling length and critical power for optical switching. The dependencies of the coupling length and critical power on the width of the gap layer and the input power levels are discussed, compared with those predicted by the coupled-mode approximations.

An eye-contact technique using a blazed half-transparent mirror (BHM) is developed. This half-transparent mirror (HM) consists of an in-line array of many slanting micro-HMs. We fabricated a prototype system and confirmed the principle of this technique. The resolution of an image reflected by a BHM was simulated to determine how to improve the image quality and the factors degrading the resolution were clarified.

This paper describes the concepts and methodologies of the INTELLITUTOR system which is an integrated intelligent programming environment for learning programming. INTELLITUTOR attempts to work as a human programming tutor to guide a user, i.e., a student, in writing a computer program, to detect logical errors within it, and to make advices not only for fixing them but also for letting him notice his misunderstandings. The system consists of three major modules, i.e., GUIDE, ALPUS and TUTOR. GUIDE is a guided editor for easy coding, ALPUS is an algorithm-based program understander, and TUTOR is an embedded-intelligent tutoring system for programming education. The ALPUS system can infer user's intentions from buggy codes in addition to detecting logical errors by means of knowledge-based reasoning. ALPUS uses four kinds of programming knowledge: 1) knowledge on algorithms, 2) Knowledge on programming techniques, 3) Knowledge on a programming language, and 4) Knowledge on logical errors. These knowledge are organized in a hierarchical procedure graph (HPG) as a multi-use knowledge base. The knowledge on logical errors was obtained by means of cognitive experiments. The student model is built by means of the results of ALPUS and interactions between a student and the system. Teaching is done based on the student model. Because the ITS subsystem, i.e., TUTOR, is embedded within the intelligent programming environment interactions for creating the student model could be minimized. Although the current system deals with the PASCAL language, most of the knowledge is applicable to those of procedure-oriented programming languages. The INTELLITUTOR system was implemented in the frame-based knowledge engineering environment ZERO and working on a UNIX workstation for system evaluation.

Mean Time Between Failures (MTBF) is an important measure of practical repairable systems, but it has not been obtained for a repairable linear consecutive-k-out-of-n: F system. We first present a general formula for the (steady-state) availability of a repairable linear consecutive-k-out-of-n: F system with nonidentical components by employing the cut set approach or a topological availability method. Second, we present a general formula for frequency of system failures of a repairable linear consecutive-k-out-of-n: F system with nonidentical components. Then the MTBF for the repairable linear consecutive-k-out-of-n: F system is shown by using the frequency of system failure and availability. Lastly, we derive some figures which show the relationship between the MTBF and repair rate µorρ(=λ/µ) in the repairable linear consecutive-k-out-of-n: F system. The figures can be easily used and are useful for reliability design.

Finding DC solutions of nonlinear networks is one of the most difficult tasks in circuit simulation, and many circuit designers experience difficulties in finding DC solutions using Newton's method. Piecewise-linear analysis has been studied to overcome this difficulty. However, efficient piecewiselinear algorithms have not been proposed for nonlinear resistive networks containing the Gummel-Poon models or the Shichman-Hodges models. In this paper, a new piecewise-linear algorithm is presented for solving nonlinear resistive networks containing these sophisticated transistor models. The basic idea of the algorithm is to exploit the special structure of the nonlinear network equations, namely, the pairwise-separability. The proposed algorithm is globally convergent and much more efficient than the conventional simplical-type piecewise-linear algorithms.

This paper presents a hypermedia English learning environment, called HELEN (Hypermedia Environment for Learning ENglish), which integrates traditional methods of learning English, audio-visual facilities for both listening and watching and intelligent tutoring functions for suitable advice to each learner based on natural language understanding. HELEN consists of an authoring stage and a learning stage. In order to support multimodal learning, at the authoring stage HELEN gets voice and video scenes from a video disc and text sentences from an image scanner, then analyzes the sentences both syntactically and semantically by a natural language processing module so that necessary information for conversation, error identification and example sentence retrieval may be extracted. Thus at the learning stage, HELEN is able to aid learners to learn hearing, reading, writing, watching, consulting and noting. Besides these facilities HELEN also supports two facilities for tests in English: One is the test facilities of dictating sentences and the other is QA (questions and answers) facilities to make learner's comprehension state clear. According to the results of these tests, HELEN identifies learner's illegal usage of syntax or semantics, and piles them in a student model. The illegal usage in the model is used as resources for generating questions, treating errors, determining topics, etc. The main part of this paper concerns with the representation method for syntax and semantics of correct and incorrect sentences.

This paper presents an experimental environment of an intelligent tutoring system called EXPITS. In this environment, users learn functions and the structure of the intelligent tutoring system and characteristics of knowledge processing. EXPITS provides facilities for investigating internal processes and internal states of the intelligent tutoring system. These facilities include visualization tools and controllers of internal processes. Because the internal states and behavior of ITS depend on student's understanding states, one cannot get total understanding of ITS without information about student's knowledge states. To solve this problem, we introduce a pseudo student which simulates a human student in order to visualize explicitly all information which affects ITS behavior. Target users of EXPITS are school teachers, who are users of intelligent tutoring systems, university students who are studying artificial intelligence and postgraduate students who are specially studying intelligent tutoring systems. We have designed EXPITS to achieve different learning objectives for these three kinds of users. The learning objective for school teachers is to understand the differnce between intelligent tutoring systems and traditional CAI systems. University students are expected to understand characteristics of knowledge processing and rule based systems. Lastly, EXPITS provides postgraduate students who are studying intelligent tutoring systems with a test bed for examining ability and efficiency of the system in different configurations by changing parameters and by replacing constituents of the system. To achieve these purposes, EXPITS has experimental facilities for the following four themes; relationship between the domain knowledge representation method and teaching activities, the selection method of teaching paradigms, relationship between problem solving processes and teaching activities, and student modeling.

Kanji Laboratory is a kanji learning ICAI system. In this paper, we describe the development of Kanji Laboratory, which is designed for foreigners who are learning Japanese kanji. We have developed Kanji Laboratory under the guidelines of environmental ICAI systems, based on a kanji learning method focusing on kanji radicals. Kanji Laboratory consists of a knowledge base, a learning environment and an advisor module. The knowledge base can well-handle the knowledge of Joyo Kanji (1,945 characters). Each one is related with its radicals via their inherited attributes. In addition, this knowledge base system can search kanji knowledge quickly. The learning environment has the following features: (1) Students can construct a kanji by combining radicals and disassemble the kanji into radicals and strokes. (2) Students can use electronic tools, such as a kanji dictionary, which support kanji learning. In this way, students can learn kanji and the relations with its radicals effectively. With regard to the advisor, although it occurs that students fall in plateaus of learning in environmental CAI, the advisor module is designed to give well-timed advice to students, avoiding those plateaus, based on the observation of their learning actions.

Optical waveguides are one of the key devices for photonic integrated circuits considered to be one of the candidates for optical interconnects. In particular lossless bend type waveguides are necessary to integrate different optical devices monolithically. In this paper, we report on the bending loss characteristics of the multi-quantum well bend waveguide with respect to the bend radius and lateral optical mode confinement. We show that to decrease the bending loss to less than 0.5 dB, it is necessary to increase either the confinement or the bend radius. For an example, when the confinement is around 85%, the bend radius should be more than 2 mm. We also show the application of the S-bend waveguides to directional coupler type optical switch.

Reflection type optical switches with intersecting waveguides and curved electrodes are newly proposed. The guided incident mode is expanded into an infinite spectrum of plane wavelets. The effects of light tunneling into the transmission port is taken care of by treating the 3-layer structure and using its reflection and transmission coefficients in estimation of the extinction ratios. It is found that the electrode curved in the form of an exponential spiral provides remarkably improved power reflectivity. This is because it poses a constant angle of incidence (smaller than the critical angle) to all variously oriented impinging wavelets. In this way, all plane wavelets are made to undertake total reflections. These total reflections result in considerably high extinction ratios to be achivable at the transmission port. It is also shown that the electrode length is shorter and the intersection angle is wider than those corresponding to a straight electrode. Therefore, it is concluded that the curvature of the electrode improves the switching characteristics of the device.