The bit error performance of a Direct Sequence Spread Spectrum Communication system in actual land mobile satellite channel is evaluated with experiments. Field test results with the ETS-V satellite in urban and suburban environments at L-band frequency show that this land mobile satellite channel of 3MHz bandwidth can be seen as a non-frequency selective Rician fading channel as well as shadowing channel. The bit error performance can be estimated from signal power measurement as in the case of narrow band modulation signals.

In multidimensional signal sampling, the orthogonal sampling scheme is the simplest one and is employed in various applications, while a non-orthogonal sampling scheme is its alternative candidate. The latter sampling scheme is used mainly in application where the reduction of the sampling rate is important. In three-dimensional (3-D) signal processing, there are two typical sampling schemes which belong to the non-orthogonal samplings; one is face-centered cubic sampling (FCCS) and the other is body-centered cubic sampling (BCCS). This paper proposes a new design method for 3-D band-limiting FIR filters required for such non-orthogonal sampling schemes. The proposed method employs the McClellan transformation technique. Unlike the usual 3-D McClellan transformation, however, the proposed design method uses 2-D prototype filters and 2-D transformation filters to obtain 3-D FIR filters. First, 3-D general sampling theory is discussed and the two types of typical non-orthogonal sampling schemes, FCCS and BCCS, are explained. Then, the proposed design method of 3-D bandlimiting filters for these sampling schemes is explained and an effective implementation of the designed filters is discussed briefly. Finally, design examples are given and the proposed method is compared with other method to show the effectiveness of our methos.

The spread spectrum system (abbreviated as SS system) is known to be an excellent communication system which resists jamming. Recently, its application to a simplified wireless communication system has been considered to be suited for consumer communication. In Japan, SS wireless LAN system has got the approval on 2.4GHz ISM band already. A compact SS transceiver for the SS wireless LAN is realized, whose data ratio is 230kbps. The SS transceiver is based on a direct sequence for the modulation, and the demodulation is carried out by a specially developed SAW device. In the first part of this paper, the technical conditions of the SS wireless LAN are mentioned. Then the SAW device and the principle of the demodulation are discussed. Finally, the configuration of the SS transceiver and the protocol of the SS wireless LAN are presented.

The Cooper pairing interaction in high Tc oxide superconductor is discussed in terms of an empirical expression; TcDexp[1/g], gcωo which was derived in our previous investigation. The dual character of this expression consisting of the phonon Debye temperature D and electronic excitation ωo in the mid-infrared region can be interpreted on the basis of the phonon-assisted mechanism on carrier conduction and the electronic excitation. A tunneling spectrum here presented shows certain evidence of the phonon contribution. The characteristics of the long range superconductive proximity phenomena recently reported are also may be interpreted by this mechanism.

This paper reviews the historical aspect of contributions on the theory of analysis and diagnosis of linear circuits, which have been made by Japanese researchers in these twenty years. On papers of diagnosis, those related to element-value solvability (or determinability) are mainly reviewed. Some important problems are suggested.

In this letter, a practical functional test method is proposed for production tests of microprocessor based sequence controllers. In our method, a controller under test is determined as a faulty one if the outputs defined in the process flowchart can not be provided from the circuit.

Intermittent chaos was observed in the silicon thyristor circuit without external elements of L and C, under the condition of ac excitation at the anode. Lorenz plot reconstructed from the experimental waveform and the numerical simulation of this kind of intermittency fairly agreed with each other.

In this letter, a new structure of adaptive IIR notch filter is presented. The structure is based on direct form realization and uses the similar adaptation algorithm given in Ref. (4). A quantitative analysis for convergence properties is developed. It is shown that the proposed structure shows superior performance comparing with previously proposed designs. The results of computer simulations are presented to substantiate the analysis.

In this paper, we present an efficient method for the fault simulation of the reconvergent fan-out stem. Our method minimizes the fault propagating region by analyzing the topology of the circuit, whose region is smaller than that of Tulip's. The efficiency of our method is illustrated by experimental results for a set of benchmark circuits.

In our recent work, a forward test generation method for sequential circuits by using a single time frame was proposed. In order to improve the effectiveness of the method, we introduced an extended mode which can handle the two time frames for a hard-to-test fault and a state escaping phase which can detect a sequence of unsuitable states for test generation. The experimental results show that the improved method is effective in generating higher coverage tests with a small number of tests.

Numerical solutions for the near-field of microstrip antennas are presented. The field distribution is calculated by taking the inverse Fourier transform involving the current distribution with the help of the spectral-domain moment method. A new technique to save the computation time is devised, and the field pattern of the circularly polarized antenna is illustrated.

The authors developed new measuring system (Holographic Pattern Measuring System [HPMS]), which is composed of both techniques of holography and graphic image processing, was used to measure the vibrations of a printed circuit board (PCB) due to operation of a mounted electromagnetic relay on it. The clear vibration patterns were obtained. By using pattern analysis processor, quantitative vibration patterns of the PCB surface were observed. Both the vibration patterns and displacements were changed by edge fixing way of the PCB.

A method to analyze two-pattern test capabilities of autonomous test pattern generator (TPG) circuits for use in built-in self-testing are described. The TPG circuits considered here include arbitrary autonomous linear sequential circuits in which outputs are directly fed out from delay elements. Based on the transition matrix of a circuit, it is shown that the number of distinct transitions in a subspace of state variables can be obtained from rank of the submatrix. The two-pattern test capabilities of LFSRs, cellular automata, and their fast parallel implementation are investigated using the transition coverage as a metric. The relationships with dual circuits and reciprocal circuits are also mentioned.

Design of high-speed digital circuits such as adders and multipliers is one of the most important issues to implement high performance VLSI systems. This paper proposes a new multiple-valued code assignment algorithm to implement locally computable combinational circuits for k-ary operations. By the decomposition of a given k-ary operation into unary operations, a code assignment algorithm for k-ary operations is developed. Partition theory usually used in the design of sequential circuits is effectively employed for optimal code assignment. Some examples are shown to demonstrate the usefulness of the proposed algorithm.

To realize next-generation high performance ULSI processors, it is a very important issue to reduce the critical delay path which is determined by a cascade chain of basic gates. To design highly parallel digital operation circuits such as an adder and a multiplier, it is difficult to find the optimal code assignment in the non-linear digital system. On the other hand, the use of the linear concept in the digital system seems to be very attractive because analytical methods can be utilized. To meet the requirement, we propose a new design method of highly parallel linear digital circuits for unary operations using the concept of a cycle and a tree. In the linear digital circuit design, the analytical method can be developed using a representation matrix, so that the search procedure for optimal locally computable circuits becomes very simple. The evaluations demonstrate the usefulness of the circuit design algorithm.

Toward the age of ultra-high-density digital ULSI systems, the development of new integrated circuits suitable for an ultimately fine geometry feature size will be an important issue. Resonant-tunneling (RT) diodes and transistors based on quantum effects in deep submicron geometry are such kinds of key devices in the next-generation ULSI systems. From this point of view, there has been considerable interests in RT diodes and transistors as functional devices for circuit applications. Especially, it has been recognized that RT functional devices with multiple peaks in the current-voltage (I-V) characteristic are inherently suitable for implementing multiple-valued circuits such as a multiple-state memory cell. However, very few types of the other multiple-valued logic circuits have been reported so far using RT devices. In this paper, a new multiple-valued programmable logic array (MVPLA) based on RT devices is proposed for the next-generation ULSI-oriented hardware implementation. The proposed MVPLA consists of 3 basic building blocks: a universal literal circuit, an AND circuit and a linear summation circuit. The universal literal circuit can be directly designed by the combination of the RT diodes with one peak in the I-V characteristic, which is programmable by adjusting the width of quantum well in each RT device. The other basic building blocks can be also designed easily using the wired logic or current-mode wired summation. As a result, a highdensity RT-diode-based MVPLA superior to the corresponding binary implementation can be realized. The device-model-based design method proposed in this paper is discussed using static characteristics of typical RT diode models.

We propose a method of diagnosing any logical fault in combinational circuits through a repetition of the single fault-net location procedure with the aid of probing, called SIFLAP-G. The basic idea of the method has been obtained through an observation that a single error generated on a fault-net often propagates to primary outputs under an individual test even though multiple fault-nets exist in the circuit under test. Therefore, candidates for each fault-net are first deduced by the erroneous path tracing under the single fault-net assumption and then the fault-net is found out of those candidates by probing. Probing internal nets is done only for some of the candidates, so that it is possible to greatly decrease the number of nets to be probed. Experimental results show that the number seems nearly proportional to the number of fault-nets (about 35 internal nets per fault-net), but almost independent of the type of faults and the circuit size.

The design of complex VLSI systems relies more and more heavily on scientific computing for numerical simulation and configuration/performance optimization. Especially, computer simulation is becoming a component of VLSI design methodology, for which a variety of computation evolutions have been accomplished for the past two decades. There are many different forms of simulation which are used for verification of VLSI design at various stages of the whole design process. They may be classified into functional or behavioral simulators, register transfer level (RTL) simulators, gate-level logic, or simply logic, simulators, timing simulator, circuit simulators, device simulator, and process simulators. Among these simulation tasks, a series of logic, timing, and circuit simulation is most strongly related to the design stage which deals with logic/electric waveform performance of VLSI circuits. This article surveys the state of the art of VLSI simulation, putting stress mainly on the domain of logic, timing, and circuit simulation, since the reader of the Transactions may be interested exclusively in this field.

This system called COKIS automatically extracts knowledge about C functions from the UNIX on-line manual by using its description paragraph and the user can interactively inquire to the system in order to know about UNIX C functions. The idea is motivated on the one side to free users from being involved in an exhaustive knowledge acquisition in the past, and to examine problems in understanding knowledge itself on the other. We propose Memory Processor which is implemented to realize extracting knowledges from corpus and processing dialogues in the inquiry system at the same modules.

In a two-layer self-diplexing antenna fed at two ports, theoretical analysis has already shown that the isolation characteristics can be improved by adjusting the angle between the feed locations of the transmitting and receiving antennas. In this letter, we experimentally investigate the isolation characteristics of the self-diplexing array antenna. First, calculated and experimental results for each feed location of the element antenna are compared and good agreement is found. Second, experimental results with a 19-element planar array indicate that a self-diplexing antenna with suitably chosen feed configuration is effective in improving the isolation in a phased array antenna.