Recent progress on the ultrahigh-speed optical transmission experiments are reviewed including the ultrashort pulse generation, high-speed timing extraction, all-optical multi/demultiplexing. Also discussed are the latest 100 Gbit/s experiments and a scope to higher bit-rate, longer distance optical transmission.

This paper advocates the use of linear objective function in analytic analog placement. The role of linear and quadratic objctive functions in the behavior and results of an analog placement algorithm based on the force directed method is discussed. Experimental results for a MCNC benchmark circuit and another one from text books are shown to demonstrate the effect of a linear and a quadratic objective function on the analog constraint satisfaction and CPU time. By introducing linear objective function to the algorithm, we obtain better placements in terms of analog constraint satisfaction and computation cost than in case of conventional quadratic objective function.

Recently, many researches on associative memories have been made a lot of neural network models have been proposed. Bidirectional Associative Memory (BAM) is one of them. The BAM uses Hebbian learning. However, unless the traning vectors are orthogonal, Hebbian learning does not guarantee the recall of all training pairs. Namely, the BAM which is trained by Hebbian learning suffers from low memory capacity. To improve the storage capacity of the BAM, Pseudo-Relaxation Learning Algorithm for BAM (PRLAB) has been proposed. However, PRLAB needs long learning epochs because of random initial weights. In this paper, we propose Quick Learning for BAM which greatly reduces learning epochs and guarantees the recall of all training pairs. In the proposed algorithm, the BAM is trained by Hebbian learning in the first stage and then trained by PRLAB. Owing to the use of Hebbian learning in the first stage, the weights are much closer to the solution space than the initial weights chosen randomly. As a result, the proposed algorithm can reduce the learning epocks. The features of the proposed algorithm are: 1) It requires much less learning epochs. 2) It guarantees the recall of all training pairs. 3) It is robust for noisy inputs. 4) The memory capacity is much larger than conventional BAM. In addition, we made clear several important chracteristics of the conventional and the proposed algorithms such as noise reduction characteristics, storage capacity and the finding of an index which relates to the noise reduction.

This report describes 4-2 compressors composed of Complementary Pass-Transistor Logic (CPL). We will show that circuit designs of the 4-2 compressors can be optimized for high speed and small size using only exclusive-OR's and multiplexers. According to a circuit simulation with 0.8µm CMOS device parameters, the maximum propagation delay and the average power consumption per unit adder are 1.32 ns and 11.6 pJ, respectively.

Resonant slots are widely used for conventional slotted waveguide array. Reflection from each slot causes a standing wave in the waveguide and beam tilting technique is essential to suppress the reflection at the antenna input port. But the slot reflection narrows the overall frequency bandwidth and the design taking it into account is complicated. This paper proposes a reflection cancelling slot pair as an array element, which consists of two slots spaced by 1/4λg. Round trip path-length difference between them is 1/2λg and reflection waves from a pair disappear and traveling-wave excitation in the waveguide is realized. The full wave analysis reveals that mutual coupling between paired slots is large and seriously reduces the radiation from a pair. Offset arrangement of slots in a pair is recommended to decrease the mutual coupling and to realize strong coupling. In practical array design, the mutual couplings from other pairs were simulated by imposing periodic boundary conditions above the aperture. To clarify the advantages of the slot pair over a conventional resonant slot, the predicted characteristics are compared. Reflection characteristics of the array using the slot pair is excellent and a boresite beam array can be realized. In addition, a slot pair can realize stronger coupling than the conventional resonant slot, while the bandwidth of the former in terms of the aperture field phase illumination is narrower than that of the latter. These suggests that the slot pair array is much more suitable for a small array than conventional one. Finally, the predicted characteristics are confirmed by experiments.

The origin of and a method of enhancing the Optical Beam Induced Resistance Change (OBIRCH) signal for defect observation in VLSI metal interconnections is discussed based on a numerical analysis of three-dimensional thermal conduction and experimental results. The numerical analysis shows that the OBIRCH signal originates from a slight increase in the resistance of the metal line caused by laser beam heating and that its effect is influenced by the temperature of the metal layer. Both simulations and experimental results suggest that cooling the sample is preferable to detect the OBIRCH signal. The decrease in the total resistance of the metal line without any change in the amount of the resistance increase under laser illumination is found to be the main cause of the OBIRCH signal enhancement under low temperature measurement.

We consider a class of unknown scenes Sk(n) with rectangular obstacles aligned with the axes such that Euclidean distance between the start point and the target is n, and any side length of each obstacle is at most k. We propose a strategy called the adaptive-bias heuristic for navigating a robot in such a scene, and analyze its efficiency. We show that a ratio of the total distance walked by a robot using the strategy to the shortest path distance between the start point and the target is at most 1+(3/5) k, if k=o(n) and if the start point and the target are at the same horizontal level. This ratio is better than a ratio obtained by any strategy previously known in the class of scenes, Sk(n), such that k=o(n).

Recently, efficient algorithms that exploit the separability of nonlinear mappings have been proposed for finding all solutions of piecewise-linear resistive circuits. In this letter, it is shown that these algorithms can be extended to circuits containing piecewise-linear resistors that are neither voltage nor current controlled. Using the parametric representation for these resistors, the circuits can be described by systems of nonlinear equations with separable mappings. This separability is effectively exploited in finding all solutions. A numerical example is given, and it is demonstrated that all solutions are computed very rapidly by the new algorithm.

An automatic tracing algorithm of the transistor-level performance faults in the waveform-based approach with CAD-linked electron beam test system which utilizes a transistor-level circuit data in CAD database is proposed. Performance faults mean some performance measure such as the temporal parameters (rise time, fall time and so on) lies outside of the specified range in a VLSI. Problems on automatic fault tracing in the transistor level are modeled by using graphs. Combinational circuits which consist of MOS transistors are considered. A single fault is assumed to be in a circuit. The algorithm utilizes Depth-First Search algorithm where faulty upstream interconnections are searched as deeply as possible. Treatment of the faults on downstream interconnections and on unmeasurable interconnections is given. Application of this algorithm to the 2k-transistor block of a CMOS circuit showed its validity in the simulation.

The scope of this paper is the realization of FIR digital filters with an emphasis on linear phase and maximally flat cases. The transfer functions of FIR digital filters are polynomials and polynomial evaluation algorithms can be utilized as realization schemes of these filters. In this paper we investigate the application of a class of polynomial evaluation algorithms called "recursive triangles" to the realization of FIR digital filters. The realization of an arbitrary transfer function using De Casteljau algorithm, a member of the recursive triangles used for evaluating Bernstein polynomials, is studied and it is shown that in some special and important cases it yields efficient modular structures. Realization of two dimensional filters based on Bernstein approximation is also considered. We also introduce recursive triangles for evaluating the power basis representation of polynomials and give a new multiplier-less maximally flat structure based on them. Finally, we generalize the structure further and show that Chebyshev polynomials can also be evaluated by the triangles. This is the triangular counterpart of the well-known Chebyshev structure. In general,the triangular structures yield highly modular digital filters that can be mapped to an array of concurrent processors resulting in high speed and effcient filtering specially for maximally flat transfer functions.

This paper proposes a buried-LATID structure featuring a peaked vertical profile around gate edge for the n- drain unlike the reported conventional LATID structure. As compared to the conventional LATID FETs, the deep-submicron buried-LATID FETs achieve improved circuit speed by 7% (50% compared to LDD FETs) due to suppressed gate-to-drain capacitance and improved lifetime by 10 times (300 times compared to LDD FETs). The buried-LATID FETs are very promising for deep-submicron MOSFETs to achieve improved performance and hot-carrier reliability at the same time.

We have studied a circuit partitioning approach in the view of parallel circuit simulation on a MIMD parallel computer. In parallel circuit simulation, a circuit is partitioned into equally sized subcircuits while minimizing the number of interconnection nodes. Besides circuit partitioning time should be short enough compared with the total simulation time. From the details of circuit simulation time, we found that balancing subcircuits is critical for low parallel processing, whereas minimizing the interconnection nodes is critical for highly parallel processing. Our circuit partitioning approach consists of four steps： Grouping transistors, initial partitioning the transistor-groups, minimizing the number of interconnection nodes, and balancing the subcircuits. It is based on an algorithmic approach, and can directly control the tradeoffs between balancing subcircuits and minimizing the interconnection nodes by adjusting the parameters. We partitioned a test circuit with 3277 transistors into 4, 9, ... , 64 subcircuits, and did parallel simulations using PARACS, our parallel circuit simulator, on an AP1000 parallel computer. The circuit partitioning time was short enough-less than 3 percent of the total simulation time. The highest performance of parallel analysis using 49 processors was 16 times that of a single processor, and that for total simulation was 9 times.

For the efficient circuit simulation, several direct/relaxation-based mixed mode simulation techniques have been studied. This paper proposes the combination of selective trace, which is well-known in the logic simulation, with dynamic network separation. In the selective trace method, the time points to be analyzed are selected for each subcircuit. Since the separation technique enables the analysis of each subcircuit independently, it is possible to skip solving the latent subcircuits, according to selective trace. Selecting the time points in accordance with activity of each subcircuit is analogous to multirate numerical integration technique used in the waveform relaxation algorithm.

This paper deals with the size of switching functions in Exclusive-OR sum-of-products expressions (ESOPs). The size is the number of products in ESOP. There are no good algorithms to find an exact minimum ESOP. Since the exact minimization algorithms take a time in double exponential order, it is almost impossible to minimize ESOPs for an arbitrary n-variable functions with n5. Then,it is necessary to study the size of some concrete functions. These concrete functions are useful for testing heuristic minimization algorithms. In this paper we present the lower bounds on size of periodic functions in ESOPs. A symmetric function is said to be periodic when the vector of weights of inputs X such that f(X)1 is periodic. We show that the size of a 2t+1-periodic function with rank r is proportional to n2t+r, where t0 and 0r2t, i.e., in polynomial order,and thet the size of a (2s+1)2t-periodic function with s0 and t0 is greater than or equal to (3/2)n-(2s+1)2t, i.e., in exponential order. The concrete function the size of which is greater than or equal to 32(3/2)n-8 is presented. This function requires the largest size among the concrete functions the sizes of which are known. Some results for non-periodic symmetric functions are also given.

IC performance simulation for statistical purpose is usually very time-consuming since the scale and complexity of IC have increased greatly in recent years. A common approach for reduction of simulation cost is aimed at the nature of simple modeling instead of actual circuit performance simulations. In this paper,a stochastic interpolation model (SIM) scheme is proposed which overcomes the drawbacks of the existing polynomial-based approximation schemes. First,the dependence of the R2press statistic upon a parameter in SIM is taken into account and by maximizing R2press this enables SIM to achieve the best approximation accuracy in the given sample points without any assumption on the sample data. Next, a sequential sampling strategy based on variance analysis is described to effectively construct SIM during its update process. In each update step, a new sample point with a maximal value of variance is added to the former set of the sample points. The update process will be continued until the desired approximation accuracy is reached. This would eventually lead to the realization of SIM with a quite small number of sample points. Finally, the coefficient of variance is introduced as another criterion for approximation accuracy check other than the R2press statistic. The effectiveness of presented implementation scheme is demonstrated by several numerical examples as well as a statistical circuit analysis example.

In order to construct a high-capacity and high-reliable indoor wireless communications system, it is essential to design the modulation/demodulation, coding and access schemes with high and variable data rate transmission capabilities, which meet the technical requirements inherent to wireless communications, i.e., high frequency utilization efficiency and robustness for fading. In this paper, we propose the frequency and time division multiple access with demand-assignment (FTDMA/DA) using multicarrier modulation as a frequency and time synchronous answer to meet the requirements, and analyze the performance of the FTDMA/DA system, taking account of teletraffic characteristics of multimedia information sources.

This paper describes a segment driver IC for high-quality liquid-crystal-displays (LCDs). Major design issues in the segment driver IC are a wide signal bandwidth and excessive output-offset variation both within a chip and between chips. After clarifying the trade-off relation between the signal bandwidth and the output-offset variation originated from conventional sample-and-hold (S/H) circuits, two wide-band S/H circuits with low output-offset variation have been introduced. The basic ideas for the proposed S/H circuits are to improve timing of the sampling pulses applied to MOS analog switches and to prevent channel charge injection onto a storage capacitor when the switches turn off. The inter-chip offset-cancellation technique has been also introduced by using an additional S/H circuit. Two test chips were implemented using the above S/H circuits for demonstration purposes. The intra-chip output-offset standard deviation of 9.5 mVrms with a 3dB bandwidth of 50 MHz was achieved. The inter-chip output-offset standard deviation was reduced to 5.1 mVrms by using the inter-chip offset-cancellation technique. The evaluation of picture quality of an LCD using the chips shows the applicability of the proposed approaches to displays used for multimedia applications.

Two types of novel nVT level shift circuits based on the square law characteristics of MOSFETs have been proposed. These circuits generate VIN+nVT or VIN-nVT (where VT is a threshold voltage), if the input voltage is applied as the VIN. These circuits can be widely used in MOSFET characterization, compensating VT effect, VT measurement, level shifting, etc. Type 1 is directly derived from the nVT-sift circuit proposed by Wang. Type 2 can reduce a total chip area than type 1 and has a wider input range. SPICE simulations show that the proposed circuits have a very wide input range and a small power consumption.

The Synchronous Optical Network (SONET) technology offers technical possibilities to build high speed transport networks and enables the operator to react quickly to the customers' capacity requirements. Furthermore the advanced SONET equipment, with standardized control and operation features, provides opportunities for new services, such as broadband services, and cost-effective ways to enhance existing services, such as network survivability improvement. But SONET technology can also create a certain degree of complexity in building cost-efficient network, especially in case of SONET Self-Healing Ring (SHR). It is a challenge for network planner to find an effective way to select the most economical SONET ring, or combination of rings, for given demands between a set of nodes that are supposed to be connected in a certain type of ring configuration. Three types of ring are standard today: path unidirectional, 2-fiber line protection bidirectional and 4-fiber line protection bidirectional. For a given network, the choosing of ring architecture based on economical considerations involves two major factors. They are capacity requirement and equipment cost. Capacity requirements of different SONET ring architectures depend upon different conditions. While facility line rate, which is a key factor in deciding what kind self-healing ring can be deployed economically on these requirements. Routing decisions play a key role in deciding the ring capacities required, especially for bidirectional rings. In the paper, we will make the economic study on how SONET SHR architecture works out with a variety of demand patterns, to find criteria for ring selection. We first present two efficient demand loading algorithms for BSHR capacity calculation, and then analyze the results from their application on a variety of demand patterns. The economic study for SONET SHR networks based on different architectures are also discussed.

An HDTV still-picture camera that uses four PAL CCD sensors has been developed for use as a high-speed, high-resolution image reader. The CCD sensors are optically coupled to a single lens by a pyramidal mirror. Each CCD sensor reads a quarter of the image and the four quarter-images are combined into one HDTV picture. Discontinuities at the lines where the four images join can be eliminated by white- and dark-level correction and gamma correction. Moreover, smoothing processing using a weighted-mean method is performed to produce a seamless picture. With this processing the camera can consistently produce seamless pictures.