A circuit emulation technique in the ATM network becomes necessary to guarantee user requirements similar to QOS grade offered by STM network where small bit error rates and constant delay times are offered. The Head-Of-Line method or other priority control schemes may be considered to provide such service in the ATM network, while it is known to give too inferior quality to non-circuit emulation service traffic. In this paper, we propose a new method called a periodical bandwidth allocation method for the circuit emulation technique. The cells of circuit emulation service traffic are transmitted periodically in our proposal. A periodical interval is determined from both the length of limit delay time of circuit emulation traffic in each switching node and the number of cell arrivals during the limit delay time. To evaluate our method, we consider three kinds of arrival patterns (the best case, the moderate case, and the worst case) for the circuit emulation traffic and a two-state MMPP for modeling the non-circuit emulation traffic. We show performance results in terms of the cell loss probability and the mean delay time in our proposal through analytic and simulation approaches.

In this paper we present an Overlapped Block Gauss-Seidel (OBGS) algorithm for the solution of large scale LSEs (Linear System of Equations) based on array architecture which we have already proposed. Better partitioning for processor array usually requires (1) balanced block size, and (2) minimum coupling between blocks for better convergence. These conditions can well be satisfied by overlapping some variables in computation algorithm. The mathematical implication of overlapped partitioning is discussed at first, and some examples show the effectiveness of OBGS algorithm. Conclusion points out that the convergence properties can well be improved by proper choice of overlapped variables. An efficient algorithm is given for choosing block and variables in order to realize above conditions.

Manipulation of Boolean functions is one of the most important techniques for implementing of VLSI logic design systems. This paper presents a fast method for generating prime-irredundant covers from Binary Decision Diagrams (BDDs), which are efficient representation of Boolean functions. Prime-irredundant covers are forms in which each cube is a prime implicant and no cube can be eliminated. This new method generates compact cube sets from BDDs directly, in contrast to the conventional cube set reduction algorithms, which commonly manipulate redundant cube sets or truth tables. Our method is based on the idea of a recursive operator, proposed by Morreale. Morreale's algorithm is also based on cube set manipulation. We found that the algorithm can be improved and rearranged to fit BDD operations efficiently. The experimental results demonstrate that our method is efficient in terms of time and space. In practical time, we can generate cube sets consisting of more than 1,000,000 literals from multi-level logic circuits which have never previously been flattened into two-level logics. Our method is more than 10 times faster than ESPRESSO in large-scale examples. It gives quasi-minimum numbers of cubes and literals. This method should find many useful applications in logic design systems.

A cyclic analog-to-digital (A/D) converter is developed which accomplishes an n-b conversion in n/2 clock cycles. The architecture consists of two 1-b quantizers connected in a loop. A CMOS design of the 1-b quantizer is given to evaluate the performance of the A/D converter when implemented using presently available process. Spice simulations and error analyses show that a resolution higher than 10-b and a sampling rate up to 1.4 Msps are attainable with a 3-µm CMOS process. A prototype converter breadboarded using discrete components has confirmed the principles of operation and error analyses. The device count and the power consumption are small compared to those of a successive-approximation A/D converter. A chip area required for the CMOS implementation is also small because only four unit capacitors are involved. Therefore, the architecture proposed herein is most suited for high accuracy, medium speed A/D conversion.

Recently, studies aiming at the next generation of visual communication services which support better human communication have been carried out intensively in Japan. The principal motive of these studies is to develop new services which are not restricted to a conventional communication framework based on the transmission of waveform signals. This paper focuses on three important key words in these studies; "intelligent," "real," and "distributed and collaborative," and describes recent research activities. The first key word "intelligent" relates to intelligent image coding. As a particular example, model-based coding of moving facial images is discussed in detail. In this method, shape change and motion of the human face is described by a small number of parameters. This feature leads to the development of new applications such as very low bit-rate transmission of moving facial images, analysis and synthesis of facial expression, human interfaces, and so on. The second key word "real" relates to communication with realistic sensations and virtual space teleconferencing. Among various component technologies, real-time reproduction of 3-D human images and a cooperative work environment with virtual space are discussed in detail. The last key word "distributed and collaborative" relates to collaborative work in a distributed work environment. The importance of visual media in collaborative work, a concept of CSCW, and requirements for realizing a distributed collaborative environment are discussed. Then, four examples of CSCW systems are briefly outlined.

Design of locally computable combinational circuits is a very important subject to implement high-speed compact arithmetic and logic circuits in VLSI systems. This paper describes a multiple-valued code assignment algorithm for the locally computable combinational circuits, when a functional specification for a unary operation is given by the mapping relationship between input and output symbols. Partition theory usually used in the design of sequential circuits is effectively employed for the fast search for the code assignment problem. Based on the partition theory, mathematical foundation is derived for the locally computable circuit design. Moreover, for permutation operations, we propose an efficient code assignment algorithm based on closed chain sets to reduce the number of combinations in search procedure. Some examples are shown to demonstrate the usefulness of the algorithm.

This paper presents Bi-CMOS current-mode multiple valued logic circuit with 1.5 V supply voltage. This circuit is composed of current mirror, threshold detector and current source. This circuit has advantages such as high accuracy, high speed, high density and low supply voltage. So, it is possible to realize high-radix multiple valued logic circuit. As an other application of the proposed circuit, a processing unit of fuzzy inference is given. This circuit operates with high speed and high accuracy. The circuit simulation of the proposed circuit has been performed using SPICE2 program.

A low-voltage, high-speed 4-bit CMOS single chip microprocessor, with instruction execution time of 1.0µs at a power supply voltage of 1.8V, has been developed. A single chip processor generally includes crystal oscillation circuits to generate a system clock or a time-base clock. But when the operating voltage is lowered, it becomes difficult to get oscillations to start reliably and to continue stably. This paper describes a low voltage circuit design method for built-in crystal oscillators. Simple design equations for oscillation starting voltage and oscillation starting time are introduced. Then effects of the circuit device parameters, such as power supply voltage, loop gain values, and subthreshold swing S, on the low voltage performance of the crystal oscillators are considered. It is shown that the crystal oscillators operate in a tailing (subthreshold) region at voltages lower than about 1.8 V. Subthreshold swing, threshold voltage, and open loop gain have a significant influence on low voltage oscillation capability. This design method can be applied to crystal oscillators for a wide range of operating voltages.

BiCMOS circuit performance at low supply voltages is discussed. The basic advantages of BiCMOS circuits are briefly reviewed, and then actual advantages of the BiCMOS gate and the BiCMOS sense circuits, which are typical BiCMOS circuits, are explained. Their advantages at low supply voltages are also discussed. BiCMOS gates, BiCMOS sense circuits, and combined circuits that include a BiCMOS sense circuit are two or three times faster than CMOS circuits down to a supply voltage of 2 V. BiCMOS circuits have high performance even at low supply voltages such as 2 V.

In this paper, a synthesizing method is proposed for the design of discrete-time cellular neural networks for binary image processing. Based on the theory of digital-logical design paradigm of threshold logic, the template parameters of the discrete-time cellular neural network for a prescribed binary image processing problem are calculated. Application examples including edge detection, connected component detection, and hole filling are given to demonstrate the merits and limitations of the proposed method. For a given realization of the parameters of the cloning template, a guideline for the selection of the offset Ic for maximum error tolerance is also considered.

With increases in frequency and density of RISC microprocessors due to rapid advances in architecture, circuit and fine device technologies, power consumption becomes a bigger concern. Supply voltage should be reduced from 5 V to 3.3 V. In this paper, several novel circuits using 0.5µm BiCMOS technology are proposed. These can be applied to a superscalar RISC microprocessor at 3.3 V power supply or below. High speed and low power consumption characteristics are achieved in a floating-point data path, an integer data path and a TLB by using the proposed circuits. The three concepts behind the proposed high speed circuit techniques at low voltage are summarized as follows. There are a number of heavy load paths in a microprocessor, and these become critical paths under low voltage conditions. To achieve high speed characteristics under heavy load conditions without increasing circuit area, low voltage swing operation of a circuit is effective. By exploiting the high conductance of a bipolar transistor, instead of using an MOS transistor, low swing operation can be got. This first concept is applied to a single-ended common-base sense circuit with low swing data lines in the register file of a floating and an integer data path. Both multi-series transistor connections and voltage drops by Vth of MOS transistors and Vbe of bipolar transistors also degrade the speed performance of a circuit. Then the second concept employed is a wired-OR logic circuit technique using bipolar transistors which is applied to a comparator in the TLB instead of multi-series transistor connections of CMOS circuits. The third concept to overcome the voltage drops by Vth and Vbe is addition of a pull up PMOS to both the path logic adder and the BiNMOS logic gate to ensure the circuits have full swing operation.

Process and device technologies of CMOS devices for low-voltage operation are described. First, optimum power-supply voltage for CMOS devices is examined in detail from the viewpoints of circuit performance, device reliability and power dissipation. As a result, it is confirmed that power-supply voltage can be reduced without any speed loss of the CMOS device. Based upon theoretical understanding, the author suggests that lowering threshold voltage and reduction of junction capacitance are indispensable for CMOS devices with low-voltage supply, in order to improve the circuit performance, as expected from MOS device scaling. Process and device technologies such as Silicon On Insulator (SOI) device, low-temperature operation and CMOS Shallow Junction Well FET (CMOS-SJET) structure are reviewed for reduction of the threshold voltage and junction capacitance which lead to high-seed operation of the COMS device at low-voltage.

This paper addresses onboard processing architecture employing direct regeneration. The advantage of direct regeneration is its hardware simplicity, even though the bit error rate performance is slightly inferior to that of demodulation-remodulation scheme with coherent detection. The channel filtering schemes as well as achievable capacities are examined by computer simulation. It is found that the system with direct regeneration has advantage in channel capacity and transmit earth station e.i.r.p. for small earth stations. A possible configuration of direct regeneration onboard in future satellite systems is proposed.

This paper describes a monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor Vbe matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within 0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of 59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0 4.2-mm2 chip integrating 36K elements, which consumes 4.0 W using a 1.0-µm-rule, 25-GHz ft, double-polysilicon self-aligned bipolar technology.

A new computer architecture using multiwavelength optoelectronic integrated circuits (OEICs) is proposed to attack the problems caused by interconnection complexity. Multiwavelength-OEIC architecures, where various wavelengths are employed as information carriers, provide the wavelength as an extra dimension of freedom for parallel processing, so that we can perform several independent computations in parallel in a single optical module using the wavelength space. This multiplex computing" enables us to reduce the wiring area required by a network and improve their complexity. In this paper, we discuss the efficient multiplexing of Batcher's bitonic sorting networks, highly parallel computing architectures that require global interconnections inherently. A systematic multiplexing of interconnection topology is presented using a binary representation of the connectivities of interconnection paths. It is shown that the wiring area can be reduced by a factor of 1/r2 using r kinds of wavelength components.

By adding a linear resistor in series with the inductor in Chua's circuit, we obtain a circuit whose state equation is topologically conjugate (i.e., equivalent) to a 21-parameter family C of continuous odd-symmetric piecewise-linear equations in R3. In particular, except for a subset of measure zero, every system or vector field belonging to the family C, can be mapped via an explicit non-singular linear transformation into this circuit, which is uniquely determined by 7 parameters. Since no circuit with less than 7 parameters has this property, this augmented circuit is called an unfolding of Chua's circuit--it is analogous to that of "unfolding a vector field" in a small neighborhood of a singular point. Our unfolding, however, is global since it applies to the entire state space R3. The significance of the unfolded Chua's Circuit is that the qualitative dynamics of every autonomous 3rd-order chaotic circuit, system, and differential equation, containing one odd-symmetric 3-segment piecewise-linear function can be mapped into this circuit, thereby making their separate analysis unnecessary. This immense power of unification reduces the investigation of the many heretofore unrelated publications on chaotic circuits and systems to the analysis of only one canonical circuit. This unified approach is illustrated by many examples selected from a zoo of more than 30 strange attractors extracted from the literature. In addition, a gallery of 18 strange attractors in full color is included to demonstrate the immensely rich and complex dynamics of this simplest among all chaotic circuits.

This paper describes the novel relaxation-based algorithm for the harmonic analysis of nonlinear circuits. First, we present Iterated Spectrum Analysis based on harmonic balance method, where the harmonic balance method is applied to every node independently. As a result, we can avoid dealing with large scale Jacobian matrices and reduce the total simulation time, compared with the conventional method based on Galerkin's procedure or the harmonic balance method. Next, we define the frequency domain latency. Furthermore, we refer to the possibility for exploitation of three types of latency, i.e., relaxation iteration latency, frequency domain latency and Newton iteration latency. And we propose the multirate-sampling technique based on the consideration of the frequency domain latency. Finally, we apply the present technique to the simple analog circuit simulation and verify its availability for the harmonic analysis.

We have proposed a new omnidirectional image sensor COPIS (COnic Projection Image Sensor) for guiding navigation of a mobile robot. Its feature is passive sensing of the omnidirectional image of the environment in real-time (at the frame rate of a TV camera) using a conic mirror. COPIS is a suitable sensor for visual navigation in real world environment with moving objects. This paper describes a method for estimating the location and the motion of the robot by detecting the azimuth of each object in the omnidirectional image. In this method, the azimuth is matched with the given environmental map. The robot can always estimate its own location and motion precisely because COPIS observes a 360 degree view around the robot even if all edges are not extracted correctly from the omnidirectional image. We also present a method to avoid collision against unknown obstacles and estimate their locations by detecting their azimuth changes while the robot is moving in the environment. Using the COPIS system, we performed several experiments in the real world.

This paper describes a novel but simple method of implementing waveform relaxation technique for bipolar circuits involving ECL gates. This method performs gate level partitioning of ECL circuits not only during the cutoff state of the input transistor but also when the input transistor is in its active state. Partitioning at all times has become possible due to the favorable property of input and output stages of ECL gates. It is shown that this method is faster than direct method even when the circuits containing only few gates is simulated. Further, it is shown that the present method is applicable to the case where the interconnections between the ECL gates is treated as lossy transmission lines.

The path diversity improvement inherent in direct sequence spread spectrum (DS/SS) signalling under multi-path propagation environments is investigated for mobile/personal radio communications systems that employ DPSK modulation. The bit error rate (BER) performance of post-demodulation selection diversity reception is theoretically analyzed in the presence of noise-only-paths in the time window for diversity combining. Results of laboratory experiments conducted to evaluate the BER performance are also presented. It is shown that the experimental results agree well with the theoretical BER.