This study investigates a two/three-dimensional (2D/3D) symbol-mapping technique that evaluates data transmission quality based on a four-level pulse-amplitude modulation (PAM-4) symbol transition. Multi-dimensional symbol transition mapping facilitates the visualization of the degree of interference (ISI). The simulation and experimental results demonstrated that the 2D symbol mapping can evaluate the PAM-4 data transmission quality degraded by ISI and visualize the equalization effect. Furthermore, potential applications of 2D mapping and its extension to 3D mapping were explored.

Although baud-rate clock and data recovery (CDR) such as Mueller-Müller (MM) CDR is adopted to ADC-based receivers (RXs), it suffers from false-lock points when the RXs handle PAM4 data pattern because of the absence of edge data. In this paper, a false-lock-aware locking scheme is proposed to address this issue. After the false-lock-aware locking scheme, a clock phase is adjusted to achieve maximum eye height by using a post-1-tap parameter for an FFE in the CDR loop. The proposed techniques are implemented in a 56-Gb/s PAM4 transceiver. A PLL uses an area-efficient “glasses-shaped” inductor. The RX comprises an AFE, a 28-GS/s 7-bit time-interleaved SAR ADC, and a DSP with a 31-tap FFE and a 1-tap DFE. A TX is based on a 7-bit DAC with a 4-tap FFE. The transceiver is fabricated in 16-nm CMOS FinFET technology, and achieves a BER of less than 1e-7 with a 30-dB loss channel. The measurement results show that the MM CDR escapes from false-lock points, and converges to near the optimum point for large eye height.

This paper proposes a low-power 100Gb/s four-level pulse amplitude modulation driver (PAM-4 Driver) based on linear distortion compensation structure for thin-film Lithium Niobate (LiNbO3) modulators, which manages to achieve high linearity in the output. The inductive peaking technology and open drain structure enable the overall circuit to achieve a 31-GHz bandwidth. With an area of 0.292 mm2, the proposed PAM-4 driver chip is designed in a 65-nm process to achieve power consumption of 37.7 mW. Post-layout simulation results show that the power efficiency is 0.37 mW/Gb/s, RLM is more than 96%, and the FOM value is 8.84.

To meet the increasing demand for high-speed communication in VLSI (very large-scale integration) systems, next-generation high-speed data transmission standards (e.g., IEEE 802.3bs and PCIe 6.0) will adopt four-level pulse amplitude modulation (PAM-4) for data coding. Although PAM-4 is spectrally efficient to mitigate inter-symbol interference caused by bandwidth-limited wired channels, it is more sensitive than conventional non-return-to-zero line coding. To evaluate the received signal quality when using adaptive coefficient settings for a PAM-4 equalizer during data transmission, we propose an eye-opening monitor technique based on machine learning. The proposed technique uses a Gaussian mixture model to classify the received PAM-4 symbols. Simulation and experimental results demonstrate the feasibility of adaptive equalization for PAM-4 coding.

In inter-data center networks where high transmission capacity and spectral efficiency are required, a 16QAM format is deployed. On the other hand, in intra-data center networks, a PAM4 format is deployed to meet the demand for a simple and low-cost transceiver configuration. For a seamless and effective connection of such heterogeneous networks without using optical-electrical-optical conversion, an all-optical modulation format conversion technique is required. In this paper, we propose an all-optical PAM4 to 16QAM modulation format conversion using nonlinear optical loop mirror. The successful conversion operation from 2 × 26.6-Gbaud PAM4 signals to a 100-Gbps class 16QAM signal is verified by numerical simulation. Compared with an ideal 16QAM signal, the power penalty of the converted 16QAM signal can be kept within 0.51dB.

This paper analyzes the effect of error propagation of decision feedback equalizer (DFE) for PAM4 based 400Gb/s Ethernet. First, an analytic model for the error propagation is proposed to estimate the probability of different burst error length due to error propagation for PAM4 link system with multi-tap TX FFE (Feed Forward Equalizer) + RX DFE architecture. After calculating the symbol error rate (SER) and bit error rate (BER) based on the probability model, the theoretical analysis about the impact of different equalizer configurations on BER is compared with the simulation results, and then BER performance with FEC (Forward Error Correction) is analyzed to evaluate the effect of DFE error propagation on PAM4 link. Finally, two FEC interleaving schemes, symbol and bit interleaving, are employed in order to reduce BER further and then the theoretical analysis and the simulation result of their performance improvement are also evaluated. Simulation results show that at most 0.52dB interleaving gain can be achieved compared with non-interleaving scheme just at a little cost in storing memory and latency. And between the two interleaving methods, symbol interleaving performs better compared with the other one from the view of tradeoff between the interleaving gain and the cost and can be applied for 400Gb/s Ethernet.

Copper (Cu) electroless plating was conducted on planar and microstructured polydimethylsiloxane (PDMS) substrates. In this study, organic thin films terminated with nitrogen (N)-containing groups, e.g. poly (dimethylaminoethyl methacrylate) brush (PDMAEMA), aminopropyl trimethoxysilane monolayer (APTES), and polydopamine (PDA) were used to anchor palladium (Pd) catalyst. While electroless plating was successfully promoted on all sample surfaces, PDMAEMA was found to achieve the best adhesion strength to the PDMS surfaces, compared to APTES- and PDA-covered PDMS substrates, due to covalent bonding, anchoring effects of polymer chains as well as high affinity of N atoms to Pd species. Our process was also successfully applied to the electroless plating of microstructured PDMS substrates.

In this paper, we propose the novel low voltage CMOS current mode reference circuit. It reduces the minimum supply voltage by consisting the subthreshold two stage operational amplifier (OPAMP) which is regarded as the combination of the proportional to absolute temperature (PTAT) and the complementary to absolute temperature (CTAT) current generators. It makes possible to implement without extra OPAMP. This proposed circuit has been designed and evaluated by SPICE simulation using TSMC 65nm CMOS process with 3.3V (2.5V over-drive) transistor option. From simulation results, the line sensitivity is as good as 0.196%/V under the condition that the range of supply voltage (VDD) is wide as 0.6V to 3.0V. The temperature coefficient is 71ppm/ under the condition that the temperature range is from -40 to 125 and VDD=0.6V. The power supply rejection ratio (PSRR) is -47.7dB when VDD=0.6V and the noise frequency is 100Hz. According to comparing the proposed circuit with prior current mode circuits, we could confirm the performance of the proposed circuit is better than that of prior circuits.

Mixed-signal integrated circuit design and simulation highly rely on behavioral models of circuit blocks. Such models are used for the validation of design specification, optimization of system topology, and behavioral synthesis using a description language, etc. However, automatic behavioral model generation is still in its early stages; in most scenarios designers are responsible for creating behavioral models manually, which is time-consuming and error prone. In this paper an automatic behavioral model generation method for switched-capacitor (SC) integrator is proposed. This technique is based on symbolic circuit modeling with approximation, by which parametric behavioral integrator model can be generated. Such parametric models can be used in circuit design subject to severe process variational. It is demonstrated that the automatically generated integrator models can accurately capture process variation effects on arbitrarily selected circuit elements; furthermore, they can be applied to behavioral simulation of SC Sigma-Delta modulators (SDMs) with acceptable accuracy and speedup. The generated models are compared to a recently proposed manually generated behavioral integrator model in several simulation settings.

A new gain enhancement technique for an operational amplifier (opamp) using a replica amplifier is presented to reduce a sensitivity of a gain mismatch between the main amplifier and the replica amplifier which limits a gain-enhancement factor in the conventional replica-amp techniques. In the proposed technique, the replica amplifier is used to only amplify an error voltage of the main amplifier. The outputs of the main amplifier and the replica amplifier are added to cancel the error voltage of the main amplifier. The proposed technique can also achieve a higher output voltage swing because the replica amplifier amplifies only the error voltage. In case of using a fully-differential common-source opamp for the main amplifier and a telescopic opamp for the replica amplifier, Monte Carlo simulation at 100 iterations shows that the proposed amplifier has almost the same gain variation with 15.5dB gain enhancement and about five times output voltage swing expanding for a supply voltage of 1.2V compared with the single closed-loop amplifier using the telescopic opamp.

A third-order low-distortion delta-sigma modulator (DSM), whose third-order noise-shaping ability is achieved by just a single opamp, is proposed. Since only one amplifier is required in the whole circuit, the designed DSM is very power efficient. To realize the adder in front of quantizer without employing the huge-power opamp, a capacitive passive adder, which is the digital-to-analog converter (DAC) array of a successive-approximation-type quantizer, is used. In addition, the feedback path timing is extended from a nonoverlapping interval for the conventional low-distortion structure to half of the clock period, so that the strict operation timing issue with regard to quantization and the dynamic element matching (DEM) logic operation can be solved. In the proposed DSM structure, the features of the unity-gain signal transfer function (STF) and finite-impulse-response (FIR) noise transfer function (NTF) are still preserved, and thus advantages such as a relaxed opamp slew rate and reduced output swing are also maintained, as with the conventional low-distortion DSM. Moreover, the memory effect in the proposed DSM is analyzed when employing the opamp sharing for integrators. The proposed third-order DSM with a 4-bit SAR ADC as the quantizer is implemented in a 90-nm CMOS process. The post-layout simulations show a 79.8-dB signal-to-noise and distortion ratio (SNDR) in the 1.875-MHz signal bandwidth (OSR=16). The active area of the circuit is 0.35mm2 and total power consumption is 2.85mW, resulting in a figure of merit (FOM) of 95 fJ/conversion-step.

A complete 4-level pulse amplitude modulation (4-PAM) serial link transceiver including a wide frequency range clock generator and clock data recovery (CDR) is proposed in this paper. A dual-loop architecture, consisting of a frequency locked loop (FLL) and a phase locked loop (PLL), is employed for the wide frequency range clocks. The generated clocks from the FLL (clock generator) and the PLL (CDR) are utilized for a transmitter clock and a receiver clock, respectively. Both FLL and PLL employ the identical voltage controlled oscillators consisting of ring-type delay-cells. To improve the frequency tuning range of the VCO, deep triode PMOS loads are utilized for each delay-cell, since the turn-on resistance of the deep triode PMOS varies substantially by the gate-voltage. As a result, fabricated in a 0.13-µm CMOS process, the proposed 4-PAM transceiver operates from 1.5 Gb/s to 9.7 Gb/s with a bit error rate of 10-12. At the maximum data-rate, the entire power dissipation of the transceiver is 254 mW, and the measured jitter of the recovered clock is 1.61 psrms.

This paper proposes a third-order low-distortion delta-sigma modulator (DSM). The third-order noise shaping is achieved by a single opamp (excluding the quantizer). In the proposed DSM structure, the timing limitation on the quantizer and dynamic element matching (DEM) logic in a conventional low-distortion structure can be relaxed from a non-overlapping interval to half of the clock period. A cyclic analog-to-digital converter with a loading-free technique is utilized as a quantizer, which shares an opamp with the active adder. The signal transfer function (STF) is preserved as unity, which means that the integrators process only the quantization noise component. As a result, the opamp used for the integrators has lower requirements, as low-distortion DSMs, on slew rate, output swing, and power consumption. The proposed third-order DSM with a 4-bit cyclic-type quantizer is implemented in a 90-nm CMOS process. Under a sampling rate of 80 MHz and oversampling ratio of 16, simulation results show that an 81.97-dB signal-to-noise and distortion ratio and an 80-dB dynamic range are achieved with 4.17-mW total power consumption. The resulting figure of merit (FOM) is 81.5 fJ/conversion-step.

A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.

A 12 Gb/s 10-level pulse amplitude modulation (PAM) serial-link transmitter was implemented using a 0.18 µm CMOS process. The proposed 10-PAM transmitter achieves a channel efficiency of 4 bit/symbol by dual-mode amplitude modulations using 10 differential-mode levels and 3 common-mode levels. The measured maximum data-rate was 12 Gb/s over 0.7-m cable and 2-cm printed circuit board (PCB) traces. The entire transmitter consumes 432 mW such that the figure of merit of the transmitter is 36 pJ/bit. The present work demonstrates the greater channel efficiency of 4 bit/symbol than the currently reported multi-level PAM transmitters.

In recent years, the number of spam emails has been dramatically increasing and spam is recognized as a serious internet threat. Most recent spam emails are being sent by bots which often operate with others in the form of a botnet, and skillful spammers try to conceal their activities from spam analyzers and spam detection technology. In addition, most spam messages contain URLs that lure spam receivers to malicious Web servers for the purpose of carrying out various cyber attacks such as malware infection, phishing attacks, etc. In order to cope with spam based attacks, there have been many efforts made towards the clustering of spam emails based on similarities between them. The spam clusters obtained from the clustering of spam emails can be used to identify the infrastructure of spam sending systems and malicious Web servers, and how they are grouped and correlate with each other, and to minimize the time needed for analyzing Web pages. Therefore, it is very important to improve the accuracy of the spam clustering as much as possible so as to analyze spam based attacks more accurately. In this paper, we present an optimized spam clustering method, called O-means, based on the K-means clustering method, which is one of the most widely used clustering methods. By examining three weeks of spam gathered in our SMTP server, we observed that the accuracy of the O-means clustering method is about 87% which is superior to the previous clustering methods. In addition, we define 12 statistical features to compare similarity between spam emails, and we determined a set of optimized features which makes the O-means clustering method more effective.

In this letter, we develop a behavioral metric with which spamming botnets can be quickly identified with respect to their residing IP blocks. Our method aims at line-speed operation without deep inspection, so only TCP/IP header fields of the passing packets are examined. However, the proposed metric yields a high-quality receiver operating characteristics (ROC), with high detection rates and low false positive rates.

An operational amplifier is one of the key functional blocks and is widely used in analog and mixed-signal circuits. For low-power consumption, many techniques such as class AB and slew-rate enhancement have been proposed. Although phase compensation is related to power consumption, it has not been clearly discussed from the viewpoint of the power consumption. In this paper, the conventional and the improved Miller compensations and the phase compensation by introducing a new zero are dicussed for low-power operational amplifiers.

In this paper, we propose a method for finding web sites whose links are hijacked by web spammers. A hijacked site is a trustworthy site that points to untrustworthy sites. To detect hijacked sites, we evaluate the trustworthiness of web sites, and examine how trustworthy sites are hijacked by untrustworthy sites in their out-neighbors. The trustworthiness is evaluated based on the difference between the white and spam scores that calculated by two modified versions of PageRank. We define two hijacked scores that measure how likely a trustworthy site is to be hijacked based on the distribution of the trustworthiness in its out-neighbors. The performance of those hijacked scores are compared using our large-scale Japanese Web archive. The results show that a better performance is obtained by the score that considers both trustworthy and untrustworthy out-neighbors, compared with the one that only considers untrustworthy out-neighbors.

A 900 mV single-stage class-AB amplifier suitable for the Switched-Opamp technique is presented. To improve the slew-limited characteristics, a Dynamic Current Source (DCS) circuit which boosts the tail currents of the amplifier is proposed. The tail current of the proposed circuit is well defined and independent of technology parameters and supply variations. The tail current of the amplifier is 40 µA with zero differential voltages, while the maximum output current is nearly 900 µA. A single-loop 3rd order Σ-Δ modulator with the proposed amplifier was designed. For a 260 mV 15.625 kHz sinusoidal input signal, the simulated dynamic range of the modulator is 89 dB.