In this paper we present eigenmode analysis of the propagation constant for a microstrip line with dummy fills on a Si CMOS substrate. The effect of dummy fills is not negligible, particularly in the millimeter-wave band, although it has been ignored below frequencies of a few GHz. The propagation constant of a microstrip line with a periodic structure on a Si CMOS substrate is analyzed by eigenmode analysis for one period of the line. The calculated propagation constant and characteristic impedance were compared with measured values for a chip fabricated by the 0.18 µm CMOS process. The agreement between the analysis and measurement was very good. The dependence of loss on the arrangement of dummy fills was also investigated by eigenmode analysis. It was found that the transmission loss becomes large when dummy fills are arranged at places where the electromagnetic field is strong.

This work focuses on a study of strain effects in resistor stress sensors fabricated on (001) silicon and their influences on the determination of piezoresistive (pi) coefficients for the precise measurements of die stresses in electronic packages. We obtained the corrected values of the pi-coefficients by considering the strain effects, without which more than 50% discrepancies may be induced.

In this paper, a soft-error-tolerant BILBO (Built-In Logic Block Observer) FF (flip-flop) is presented. The proposed FF works as a soft-error-tolerant FF in system operations and as a BILBO FF in manufacturing testing. The construction of the proposed FF is based on that of an existing soft-error-tolerant FF, namely a BISER (Built-In Soft Error Resilience) FF. The proposed FF contains a reconfigurable C-element with XNOR calculation capability, which works as a C-element for soft-error-tolerance during system operations and as an XNOR gate employed in linear feedback shift registers (LFSRs) during manufacturing testing. The evaluation results shown in this paper indicate that the area of the proposed FF is 8.5% smaller than that of a simple combination of the existing BISER and BILBO FFs. In addition, the sum of CLK-Q delay and D-CLK setup times on system operations for the proposed FF is 19.7% shorter than that for the combination.

We studied the interaction of Bis-diethylaminosilane (SiH2[N(C2H5)2]2, BDEAS) with a hydroxylized Si (001) surface for SiO2 thin-film growth using density functional theory (DFT). BDEAS was adsorbed on the Si surface and reacted with the H atom of hydroxyl (-OH) to produce the di-ethylaminosilane (-SiH2[N(C2H5)2], DEAS) group and di-ethylamine (NH(C2H5)2, DEA). Then, DEAS was able to react with another H atom of -OH to produce DEA and to form the O-(SiH2)-O bond at the inter-dimer, inter-row, or intra-dimer site. Among the three different sites, the intra-dimer site was the most probable when it came to forming the O-(SiH2)-O bond.

We investigated the effects of various field plate and buried gate structures on the DC and small signal characteristics of 4H-silicon carbide (SiC) metal-semiconductor field-effect transistors (MESFETs). In comparison with the source-connected field plate, the gate-connected field plate exhibited superior frequency response while having similar DC characteristics. In order to further enhance the output power, dual field plates were employed in conjunction with a buried gate structure.

In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9 eV) and Yb (2.7 eV). Pt (10-20 nm)/Hf, Yb (0-10 nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of PtxHf1 - xSi formed at 400/60 min annealing in N2, SBH for electron was reduced from 0.85 eV to 0.53 eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

Joint source-channel coding (JSCC) is a method to jointly allocate the given total transmission bitrate to the source coding and channel coding to maximize the video quality at the receiving end. In this paper, we propose a practical model for efficiently determining a near-optimal code rate for JSCC in real-time video communications. The conventional code rate decision schemes using analytical source coding distortion model and channel-induced distortion model are usually complex, and typically employ the process of model parameter training which involves potentially high computational complexity and implementation cost. To avoid the complex modeling procedure, we introduce a very simple video quality model based on the playable bitrate which is defined as the total bit amount per unit time that is not affected by the channel loss during transmission including correctly recovered bits by the channel decoder. Because the video quality at the receiving end is clearly commensurate with the playable bitrate, we can easily determine the quality-oriented near-optimal code rate by finding the code rate that maximizes the playable bitrate at the sender side. The proposed playable bitrate model is very simple because it does not require the complex training procedure for obtaining model parameters, which is usually required in the conventional code rate decision method. It is shown by simulations that the proposed code rate decision scheme based on the playable bitrate model can efficiently determine the near-optimal code rate for JSCC in terms of high accuracy on the optimal code rate.

We have demonstrated the inverter operation of stacked-structure CMOS devices using pentacene and ZnO as active layers. The fabrication process of the device is as follows: A top-gate-type ZnO thin-film transistor (TFT), working as an n-channel transistor, was formed on a glass substrate. Then, a bottom-gate-type pentacene TFT, as a p-channel transistor, was fabricated on top of the ZnO TFT while sharing a common gate electrode. For both TFTs, solution-processed silicone-resin layers were used as gate dielectrics. The stacked-structure CMOS has several advantages, for example, easy patterning of active material, compact device area per stage and short interconnection length, as compared with the planar configuration in a conventional CMOS circuit.

Constructing degree-optimized resilient Boolean functions with high nonlinearity is a significant study area in Boolean functions. In this letter, we provide a construction of degree-optimized n-variable (n odd and n ≥ 35) resilient Boolean functions, and it is shown that the resultant functions achieve the currently best known nonlinearity.

This paper describes a nonlinear filter that can extract the image feature from noise corrupted image labeled self-quotient ε-filter (SQEF). SQEF is an improved self-quotient filter (SQF) to extract the image feature from noise corrupted image. Although SQF is a simple approach for feature extraction from the images, it is difficult to extract the feature when the image includes noise. On the other hand, SQEF can extract the image feature not only from clear images but also from noise corrupted images with uniform noise, Gaussian noise and impulse noise. We show the algorithm of SQEF and describe its feature when it is applied to uniform noise corrupted image, Gaussian noise corrupted image and impulse noise corrupted image. Experimental results are also shown to confirm the effectiveness of the proposed method.

This paper establishes a new unified method for fixed-length source coding problems of general sources. Specifically, we introduce an alternative definition of the smooth Renyi entropy of order zero, and show a unified approach to present the fixed-length coding rate in terms of this information quantity. Our definition of the smooth Renyi entropy has a clear operational meaning, and hence is easy to calculate for finite block lengths. Further, we represent various ε-source coding rate and the strong converse property for general sources in terms of the smooth Renyi entropy, and compare them with the results obtained by Han and Renner et al.

In this paper, we propose a two-step error concealment algorithm based on an error resilient three-dimensional discrete wavelet transform (3-D DWT) video coding scheme. The proposed scheme consists of an error-resilient encoder duplicating the lowest sub-band bit-streams for dispersive grouped frames and an error concealment decoder. The error concealment method of this decoder is decomposed of two steps, the first step is replacement of erroneous coefficients in the lowest sub-band by the duplicated coefficients, and the second step is interpolation of the missing wavelet coefficients by minimum mean square error (MMSE) estimation. The proposed scheme can achieve robust transmission over unreliable channels. Experimental results provide performance comparisons in terms of peak signal-to-noise ratio (PSNR) and demonstrate increased performances compared to state-of-the-art error concealment schemes.

Hydrogenated polymorphous Silicon allows to fabricate TFTs with very interesting characteristics including better threshold voltage stability than a-Si TFTs, lower leakage current than µc-Si:H TFTs and excellent uniformity. Investigation of threshold voltage shift mechanisms of pm-Si:H TFTs has shown a specific semiconductor material degradation with different activation energies compared to a-Si:H TFTs. TEM analysis has evidenced for the first time a significant structural difference between pm-Si:H and a-Si:H materials, in the TFT device configuration. Pm-Si:H appears to be very suitable for low cost and high performance AM-OLED fabrication.

In this letter, we propose a new tuning method of ε value, which is a parameter in the ε-filter, using a metric between signal distributions, i.e., Hellinger distance. The difference between the input and output signals is evaluated using Hellinger distance and used for the parameter tuning in the proposed method.

This paper proposes a printed tag antenna for the universal ultra-high frequency (UHF) radio frequency identification (RFID) band (860-960 MHz) using the R2R process. To widen impedance bandwidth, a π-shaped matching network is suggested. The overall dimension of the proposed tag antenna is 83.4 mm 30.2 mm and it has a gain of over 1 dBi for the entire UHF RFID band. The performances of the proposed tag antenna, printed with conductivity silver ink using an R2R process, are compared with those of a copper antenna.

An analog pre-distortion linearizer employing a radio frequency (RF) transistor with a self base bias control circuit is proposed. The self base bias control circuit extracts the envelope from the modulated input RF signal of the RF transistor and automatically controls its base current according to the extracted envelope. As a result, the proposed linearizer realizes positive gain deviation at high input power level. By adding a resistor between the RF transistor and the self base bias control circuit, the negative gain deviation can be derived. The design of the proposed lineaizer is described with taking the envelope frequency response of the self base bias control circuit into consideration. The fabricated linearizer achieves the adjacent channel power leakage ratio (ACLR) improvement of 8.1 dB for a 2 GHz-band, 10 W-class GaAs FET high-power amplifier (HPA) with negative gain deviation for W-CDMA base stations. It also achieves the ACLR improvement of 8.3 dB for a LDMOS HPA with positive gain deviation for the same application.

This paper proposes a concept of a concurrent configuration of radio-frequency (RF) micromachined and micro-electro-mechanical-system (MEMS) devices. The devices are fabricated on an originally developed dielectric-air-metal (DAM) structure that suits for fabrication of various devices all together. The DAM structure can propose membrane-supported hollow elements embedded in a silicon wafer by creating cavities in it. Even though the devices have different cavity depths, they are processed by just one planarization. In addition, since the structure is worked only from the front side of the wafer, no flipping process as well as no wafer bonding process is required, and the fact realizes low-cost concurrent integration. As applications of the DAM structures, a hollow grounded co-planar waveguide, lumped element circuitries, and an MEMS switch are demonstrated.

In this paper, a fully integrated 5 GHz voltage controlled oscillator (VCO) is presented. The VCO is designed with 0.18 µm silicon complementary metal oxide semiconductor (Si-CMOS) process. To achieve low phase noise, a novel varactors pair circuit is proposed to cancel effects of capacitance fluctuation that makes harmonic currents which increase phase noise of VCO. The VCO with the proposed varactor circuit has tuning range from 5.1 GHz to 6.1 GHz (relative value of 17.9%) and phase noise of lower than -110.8 dBc/Hz at 1 MHz offset over the full tuning range. Figure-of-merit-with-tuning-range (FOMT) of the proposed VCO is -182 dBc/Hz.

The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al2O3 and SiO2 stacked tunneling layers were investigated. The electron and hole drifts in the Si3N4 layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO2 and Al2O3 stacked tunneling layers.

We have fabricated VDP (van der Pauw) stress sensors on (111) silicon surfaces. This work focuses on a study of strain effects in VDP stress sensors, which were generally ignored in previous works, for the precise measurements of die stresses in electronic packages. The stress sensitivity was observed to be approximately 10% larger for p-type VDP sensors compared to n-type VDP sensors.