The performance of radio frequency integrated circuits (RFICs) in silicon-on-insulator (SOI) technology can be improved by using a high-resistivity SOI substrate. We investigated the correlation between substrate resistivity and the performance of a low noise amplifier (LNA) on ELTRAN(R) SOI-Epi wafersTM, whose resistivity can be controlled precisely. The use of high-resistivity ELTRAN wafers improves the Q-factor of spiral inductors, and thereby increases the gain and narrows the bandwidth of the LNA. Using the high-resistivity ELTRAN wafers, we have successfully fabricated a 2.4-GHz and 5-GHz CMOS LNA in 0.35-µm SOI CMOS technology, whose process cost is lower than the latest CMOS technologies.

The effect of the silicone vapor on the reliability of the micro-motor was examined. Adsorbed silicone was decomposed to SiO2 by heating due to the discharge between brush and commutator surface. It was found that the operation time until the failure was extremely shortened by the formation of SiO2. The existence of the maximum operation time until the failure was found as depending on the number of revolution. For the higher revolution, many amounts of SiO2 accumulated by the decomposition of the silicone shorten the operation time. For lower revolution, as the torque of the motor reduces, the operation time also shortens. Therefore, the maximum operation time exists for optimum revolution.

We have developed a low-power, high-performance MPEG-4 codec LSI for mobile video applications. This codec LSI is capable of up to CIF 30-fps encoding, making it suitable for various visual applications. The measured power consumption of the codec core was 9 mW for QCIF 15-fps codec operation and 38 mW for CIF 30-fps encoding. To provide an error-robust MPEG-4 codec, we implemented an error-resilience function in the LSI. We describe the techniques that have enabled low power consumption and high performance and discuss our test results.

A method of error concealment for JPEG2000 images is proposed in this paper. The proposed method uses the layer structure that is a feature of the JPEG2000. The most significant layer is hidden in the lowest layer of the JPEG2000 bit stream, and this embedded layer is used for error concealment. The most significant layer is duplicated because JPEG2000 uses bit-plane coding. In this coding, when the upper layers are affected by errors, the coefficients of the lower layers become meaningless. A bit stream encoded using the proposed method has the same data structure as a standard JPEG2000. Therefore, it can be decoded by a standard decoder. Our simulation results demonstrated the effectiveness of the proposed method.

New physical models, algorithms, and parameters are needed to accurately model emerging silicon-on-insulator (SOI) devices. The modeling approaches for various emerging SOI technologies are discussed in this paper.

This paper proposes a silence compression algorithm operating at multi-rates (MR) and with dual-bandwidths (DB), a narrowband and a wideband, for the MPEG (Moving Picture Experts Group)-4 CELP (Code Excited Linear Prediction) standard. The MR/DB operations are implemented by a Variable-Frame-size/Dual-Bandwidth Voice Activity Detection (VF/DB-VAD) module with bandwidth conversions of the input signal, and a Variable-Frame-size Comfort Noise Generator (VF-CNG) module. The CNG module adaptively smoothes the Root Mean Square (RMS) value of the input signal to improve the coding quality during transition periods. The algorithm also employs a Dual-Rate Discontinuous Transmission (DR-DTX) module to reduce an average transmission bitrate during silence periods. Subjective test results show that the proposed silence compression algorithm gives no degradation in coding quality for clean and noisy speech signals. These signals include about 20 to 30% non-speech frames and the average transmission bitrates are reduced by 20 to 40%. The proposed algorithm has been adopted as a part of the ISO/IEC MPEG-4 CELP version 2 standard.

In this work, we review our recent efforts to make effective use of atomistic calculations for the advancement of VLSI process simulation. We focus on three example applications: the behavior of implanted fluorine, arsenic diffusion and activation, and the impact of charge interactions on doping fluctuations.

In this work it is shown for the first time how to calculate in advance by momentum-based noise simulation for stationary Monte Carlo (MC) device simulations the CPU time, which is necessary to achieve a predefined error level. In addition, analytical expressions for the simulation-time factor of terminal current estimation are given. Without further improvements of the MC algorithm MC simulations of small terminal currents are found to be often prohibitively CPU intensive.

Nowadays, silicon technologies with feature sizes around 100 nm are used in the microelectronics industry to produce gigabits integrated circuits. The prime part of numerical simulation in their development is now well established. One of the purpose of the numerical analyses is the improvement of the mechanical reliability. We synthetize in this paper various works we have performed on the macroscopical modeling and simulation of stress problems and their effects in silicon technologies.

This paper presents an effective approach for estimating of the load matching conditions for dielectric barrier discharge (DBD) load. By the simulation method proposed here, optimal working frequency and optimal applied voltage for driving of DBD load can be calculated. Estimation results for the DBD ultraviolet generation lamp as a load of series resonant inverter are presented here, together with their evaluations.

In this letter, we propose a two-stage object-based error-concealment technique for MPEG-2 video transmitted in a burst-packet-loss environment. A burst packet loss typically destroys a large area of MPEG-2 coded video. In the first stage, the missing area is intra-picture estimated and concealed in terms of a region-based approach. In the second stage, irregular-moving objects with respect to the background are identified and compensated from the predictive picture. As compared with conventional concealment approaches, the proposed method achieves better PSNR performance and reduces the visual artifacts.

The radio-frequency thermal noise in fully-depleted (FD) silicon-on-insulator (SOI) MOSFETs and bulk MOSFETs is theoretically examined using a distributed-transmission-line model. It is shown that the thermal noise in a scaled-down SOI MOSFET is basically smaller than that in a scaled-down bulk MOSFET in a wide frequency range. In the radio-frequency range, parasitic resistances in source and drain don't yield a remarkable contribution to the difference in output thermal noise power between scaled-down bulk MOSFETs and scaled-down SOI MOSFETs. However, the output thermal noise of scaled-down SOI MOSFETs with a finite parasitic resistance is smaller than that of scaled-down bulk MOSFETs because of smaller channel capacitance.

This paper reviews the advantages of the silicon three-dimensional MMIC technology such as low loss transmission lines, high integration level, and high Q-factor on-chip inductors. Coupled to the masterslice concept, this technology also offers simple design procedure, short turn-around-time, low cost, and potential integration with LSI circuits. A K-band amplifier and an up-converter demonstrate the high frequency operation and low-power consumption benefits of the Si 3-D MMIC technology. A C-band Si-bipolar single-chip transceiver is proposed to illustrate the high integration level offered by the masterslice concept. Finally, the recent advances we achieved toward high Q-factor on-chip inductors provide the design of the S-band low noise amplifier presented in this paper.

The mesoporous materials from the self-assembled organic-inorganic compound materials have great possibilities for a variety of applications. However, to make use of these kinds of materials effectively, they must be controlled. In this paper, we are succeeded in powder state pore size control and in significantly fabrication film state for device application use.

This paper describes a new approach to the digital watermarking of motion pictures dedicatedly for the MPEG-4 video coding, which intends to enhance the error detection ability. The conventional method lacks not only the detection ability but also the compatibility with video decoders widely used today. Thus in this approach the digital watermarks are to be embedded into the quantized DCT (Discrete Cosine Transform) coefficients for the error detection, where the prevention of the picture quality degradation is also attempted. Experimental results are shown to demonstrate that the error detection ability of the proposed approach is significantly improved, as compared with that of the conventional method, and that the degradation of the picture quality by the watermarking is extremely small.

Self-ordered mesoporous silicate films from organic-inorganic compound materials are successfully fabricated into the surface photo voltage (SPV) type gas sensor device as a gas adsorption insulator layer. These kinds of gas sensors device exhibit NO gas sensing property dependent on their mesoporous film structure. We are succeeded in indication about a possibility of mesoporous silicate film for the SPV type gas sensor application.

We report on the analysis and fabrication of vertical PtSi Schottky source/drain metal oxide semiconductor field effect transistors (MOSFETs), which are suitable for combination with quantum effect devices such as resonant tunneling diodes. Analysis was carried out by one-dimensional approximation of the device structure, WKB approximation of the tunneling probability in Schottky barrier tunneling and self-consistent calculation. Theoretical calculation showed good drivability (750 µA/µm) of this device with tOX = 1 nm and tSi = 5 nm. As a preliminary experiment, devices with a Si channel thickness of 8 nm, 20 nm or 30 nm and a vertical channel length of 55 nm were fabricated. Although the drain current at the "on" state was small due to the thick gate oxide of 8 nm, analysis and measurement showed reasonable agreement with respect to the drivability. Based on the results of theoretical analysis, the device drivability can be much improved by reducing the gate oxide thickness.

A uniform raised-salicide technology has been investigated using both uniform selective-epitaxial-growth (SEG) silicon and salicide films, to reduce a junction leakage current of shallow source/drain (S/D) regions for high-performance CMOS devices. The uniform SEG-Si film without pits is formed by using a wet process, which is a carbon-free oxide removal only using a dilute hydrofluoric acid (DHF) dipping, prior to the Si-SEG process. After a titanium-salicide formation using a conventional two-step salicide process, this uniform SEG-Si film achieves good S/D junction characteristics. The uniform titanium-salicide film without bowing into a silicon is formed by a smaller Ti/SEG-Si thickness ratio, which results in a low sheet resistance of 5 Ω/sq. without a narrow-line effect. Furthermore, the drive current is maximized by this raised-salicide film using a Ti/SEG-Si thickness ratio of 1.0.

A practical method of measuring the contact resistance of a phosphorus-doped poly-Si plug formed on a lightly phosphorus-doped diffusion region in DRAM memory cells is described. Contact resistance was obtained electrically, using ordinary contact-chain test structures, by changing the measurement of the substrate bias. This separated the bias-dependent resistance of the lightly doped diffusion layer from the total resistance. The method was used experimentally to evaluate the feasibility of forming low-resistance contacts down to a diameter of 130 nm for giga-bit DRAMs. Electrical measurement showed that reducing the interface resistance between the poly-Si plug and the lightly doped diffusion layer was effective for forming low-resistance contacts, though a specific interface layer could not be detected by TEM observation.

We describe hybrid integration technologies that employ silica-based planar lightwave circuit (PLC) platforms, and report several high-performance optical components based on these technologies. First, we describe the requirements for optical integrated circuits. Then, we discuss the technologies used in hybrid integration, namely optical coupling between a semiconductor optical device and a silica waveguide, electrical signal transmission to the semiconductor optical device, and high quality optical signal processing. In addition, we describe optical integrated circuits developed for short- and long-haul networks. We realized these high-performance integrated components by combining appropriate hybrid integration technologies.